FAN53168MTC FAIRCHILD [Fairchild Semiconductor], FAN53168MTC Datasheet - Page 14

• Manufacturer Part Number: FAN53168MTC
• Description: 6-Bit VID Controlled 2-4 Phase DC-DC Controller
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

FAN53168
To provide the best accuracy for the sensing of current, the
CSA has been designed to have a low offset input voltage.
Also, the sensing gain is determined by external resistors so
that it can be made extremely accurate.
Active Impedance Control Mode
For controlling the dynamic output voltage droop as a func-
tion of output current, a signal proportional to the total out-
put current at the CSCOMP pin can be scaled to be equal to
the droop impedance of the regulator times the output cur-
rent. This droop voltage is then used to set the input control
voltage to the system. The droop voltage is subtracted from
the DAC reference input voltage directly to tell the error
amplifier where the output voltage should be. This differs
from previous implementations and allows enhanced feed-
forward response.
Current Control Mode and Thermal Balance
The FAN53168 has individual inputs for each phase which
are used for monitoring the current in each phase. This infor-
mation is combined with an internal ramp to create a current
balancing feedback system that has been optimized for initial
current balance accuracy and dynamic thermal balancing
during operation. This current balance information is inde-
pendent of the average output current information used for
positioning described previously.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It is also monitors the
supply voltage for feed-forward control for changes in the
supply. A resistor connected from the power input voltage to
the RAMPADJ pin determines the slope of the internal
PWM ramp. Detailed information about programming the
ramp is given in the applications section.
External resistors can be placed in series with individual
phases to create an intentional current imbalance if desired,
such as when one phase may have better cooling and can
support higher currents. Resistors R
the typical application circuit in Figure 1) can be used for
adjusting thermal balance. It is best to have the ability to add
these resistors during the initial design, so make sure place-
holders are provided in the layout.
Voltage Control Mode
A high gain-bandwidth voltage mode error amplifier is used
for the voltage-mode control loop. The control input voltage
to the positive input is set via the VID 6-bit logic code
according to the voltages listed in Table 1. This voltage is
also offset by the droop voltage for active positioning of the
output voltage as a function of current, commonly known as
14
SW1
through R
SW4
(see
Ω
active voltage positioning. The output of the amplifier is the
COMP pin, which sets the termination voltage for the inter-
nal PWM ramps.
The negative input (FB) is tied to the output sense location
with a resistor R
output voltage at this point. A current source from the FB pin
flowing through R
voltage from the VID voltage. The no-load voltage will be
negative with respect to the VID DAC. The main loop com-
pensation is incorporated in the feedback network between
FB and COMP.
Soft-start
The power-on ramp up time of the output voltage is set with
a capacitor and resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current
limit latch off time as explained in the following section. In
UVLO or when EN is a logic low, the DELAY pin is held at
ground. After the UVLO threshold is reached and EN is a
logic high, the DELAY cap is charged up with an internal
20µA current source. The output voltage follows the ramp-
ing voltage on the DELAY pin, limiting the inrush current.
The soft-start time depends on the value of VID DAC and
C
cations section for detailed information on setting C
When the PWRGD threshold is reached, the soft-start cycle
is stopped and the DELAY pin is pulled up to 3V. This
ensures that the output voltage is at the VID voltage when
the PWRGD signals to the system that the output voltage is
good. If EN is taken low or VCC drops below UVLO, the
DELAY cap is reset to ground to be ready for another soft
start cycle. Figure 2 shows a typical start-up sequence for the
FAN53168.
Current Limit, Short Circuit and Latch-off
Protection
The FAN53168 compares a programmable current limit set
point to the voltage from the output of the current senseam-
plifier. The level of current limit is set with the resistor from
the ILIMIT pin to ground. During normal operation, the volt-
age on ILIMIT is 3V. The current through the external resis-
tor is internally scaled to give a current limit threshold of
10.4mV/µA. If the difference in voltage between CSREF
and CSCOMP rises above the current limit threshold, the
internal current limit amplifier will control the internal
COMP voltage to maintain the average output current at
the limit.
DLY
, with a secondary effect from R
B
and is used for sensing and controlling the
B
is used for setting the no-load offset
PRODUCT SPECIFICATION
DLY
. Refer to the appli-
REV. 1.0.0 6/9/03
DLY
.