TE28F200B5T80 INTEL [Intel Corporation], TE28F200B5T80 Datasheet - Page 19

• Manufacturer Part Number: TE28F200B5T80
• Description: SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT
• Manufacturer: INTEL [Intel Corporation]

ADDRESS
BA = Block Address
IA = Identifier Address
PA = Program Address
X = Don’t Care
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
Code Device Mode
Read Array
Intelligent Identifier
Read Status Register
Clear Status Register
Word/Byte Program
Block Erase/Confirm
Erase Suspend
Erase Resume
50
90
ADVANCE INFORMATION
Bus operations are defined in Tables 3 and 4.
IA = Identifier Address: A
SRD - Data read from Status Register.
IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and
device codes.
BA = Address within the block being erased.
PA = Address to be programmed. PD = Data to be programmed at location PA.
Either 40H or 10H commands is valid.
When writing commands to the device, the upper data bus [DQ
draw.
Clear Status
Command
Intelligent
Identifier
Register
The WSM can only set the program status and erase status bits in the status
register to “1”; it cannot clear them to “0.”
The status register operates in this fashion for two reasons. The first is to give the
host CPU the flexibility to read the status bits at any time. Second, when
programming a string of bytes, a single status register query after programming the
string may be more efficient, since it will return the accumulated error status of the
entire string. See Section 3.2.3.1.
Puts the device into the intelligent identifier read mode, so that reading the device
will output the manufacturer and device codes. (A
A
Table 5. Command Codes and Descriptions (Continued)
0
0
= 0 for manufacturer code, A
= 1 for device, all other address inputs are ignored). See Section 3.2.2.
Note
2,4
6,7
Table 6. Command Bus Definitions
3
3
5
DATA
SRD = Status Register Data
IID = Identifier Data
PD = Program Data
Oper
Write
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
0
= 1 for device code.
Addr
PA
BA
X
X
X
X
X
X
SMART 5 BOOT BLOCK MEMORY FAMILY
8
–DQ
Description
15
40H/10H
] = X which is either V
Data
FFH
B0H
D0H
90H
70H
50H
20H
0
= 0 for manufacturer,
Read
Read
Oper
Write
Write
Second Bus Cycle
IL
or V
IH
Addr
PA
BA
, to minimize current
IA
X
Data
SRD
D0H
IID
PD
19