TE28F200B5T80 INTEL [Intel Corporation], TE28F200B5T80 Datasheet - Page 10

• Manufacturer Part Number: TE28F200B5T80
• Description: SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT
• Manufacturer: INTEL [Intel Corporation]

SMART 5 BOOT BLOCK MEMORY FAMILY
2.3
The
asymmetrically-blocked
system memory integration. Each erase block can
be erased independently of the others up to
100,000 times for commercial temperature or up to
10,000 times for extended temperature. The block
sizes
functionality for common applications of nonvolatile
storage. The combination of block sizes in the boot
block architecture allow the integration of several
memories into a single chip. For the address
locations of the blocks, see the memory maps in
Figures 4, 5, 6 and 7.
2.3.1
The boot block is intended to replace a dedicated
boot PROM in a microprocessor or microcontroller-
based system. The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T
suffix) or the bottom (-B suffix) of the address map
to accommodate different microprocessor protocols
for boot code location. This boot block features
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot block is
controlled using a combination of the V
WP# pins, as is detailed in Section 3.3.
10
boot
have
Memory Blocking Organization
ONE 16-KB BOOT BLOCK
block
been
WE#
WP#
RP#
V
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
PP
Figure 3. 40-Lead TSOP Pinout Diagram (Available in 4-Mbit Only)
16
15
14
13
12
11
18
9
8
7
6
5
4
3
2
1
product
chosen
architecture
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
family
to
optimize
features
PP
, RP#, and
providing
10 mmx 20 mm
40-Lead TSOP
their
Boot Block
TOP VIEW
an
28F004B5
2.3.2
Each boot block component contains two parameter
blocks of 8 Kbytes (8,192 bytes) each to facilitate
storage of frequently updated small parameters that
would normally require an EEPROM. By using
software techniques, the byte-rewrite functionality
of EEPROMs can be emulated. These techniques
are detailed in Intel’s application note, AP-604
Using Intel’s Boot Block Flash Memory Parameter
Blocks to Replace EEPROM . The parameter blocks
are not write-protectable.
2.3.3
After the allocation of address space to the boot
and parameter blocks, the remainder is divided into
main blocks for data or code storage. Each device
contains one 96-Kbyte (98,304 byte) block and
additional 128-Kbyte (131,072 byte) blocks. The
2-Mbit has one 128-KB block; the 4-Mbit, three; and
the 8-Mbit, seven.
ADVANCE INFORMATION
TWO 8-KB PARAMETER BLOCKS
MAIN BLOCKS - ONE 96-KB +
ADDITIONAL 128-KB BLOCKS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
GND
NC
NC
A
DQ
DQ
DQ
DQ
V
V
NC
DQ
DQ
DQ
DQ
OE#
GND
CE#
A
CC
CC
17
10
0
7
6
5
4
3
2
1
0