HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 29

• Manufacturer Part Number: HYB18T512161B2F-20/25
• Description: 512-Mbit x16 DDR2 SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

6
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Parameter
Operating Current - One bank Active - Precharge
t
Address and control inputs are switching; Databus inputs are switching.
Operating Current - One bank Active - Read - Precharge
I
CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are
switching; Databus inputs are switching.
Precharge Power-Down Current
All banks idle; CKE is LOW;
are floating
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Data bus inputs are switching
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Data bus inputs are floating.
Active Power-Down Current
All banks open;
inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
Active Power-Down Current
All banks open;
inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
All banks open;
commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
switching; Data Bus inputs are switching;
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
=
switching; Data Bus inputs are switching;
Burst Refresh Current
t
commands, Other control and address inputs are switching, Data bus inputs are switching.
Distributed Refresh Current
t
valid commands, Other control and address inputs are switching, Data bus inputs are switching.
CK
RAS.MAX.(IDD)
CK
CK
OUT
t
RAS.MAX(IDD)
=
=
=
= 0 mA, BL = 4,
t
t
t
CK(IDD)
CK(IDD)
CK(IDD)
.
, Refresh command every
,
,
, Refresh command every
t
t
,
RP
RC
t
RP
t
t
t
CK
=
=
CK
CK
=
t
t
=
RP(IDD)
RC(IDD)
=
=
t
Specifications and Conditions
RP(IDD)
t
t
t
t
CK
CK(IDD)
CK(IDD)
CK(IDD)
=
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
,
t
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
t
RAS
CK(IDD)
;
t
, CKE is LOW; Other control and address inputs are stable; Data bus
, CKE is LOW; Other control and address inputs are stable, Data bus
CK
t
RAS
.
=
=
t
,
=
t
RAS.MIN(IDD)
CK(IDD)
t
t
RC
RAS.MAX(IDD)
t
=
RFC
t
REFI
t
;Other control and address inputs are stable; Data bus inputs
RC(IDD)
t
CK
I
t
=
OUT
CK
= 7.8 μs interval, CKE is LOW and CS is HIGH between
, CKE is HIGH, CS is HIGH between valid commands.
t
=
RFC(IDD)
=
t
,
,
= 0 mA.
CK(IDD)
t
t
t
CK(IDD)
RP
RAS
=
interval, CKE is HIGH, CS is HIGH between valid
=
; Other control and address inputs are switching,
t
RP(IDD)
; Other control and address inputs are stable,
t
RAS.MIN(IDD)
; CKE is HIGH, CS is HIGH between valid
29
,
t
RCD
=
t
RCD(IDD)
(IDD)
(IDD)
512-Mbit Double-Data-Rate-Two SDRAM
;
, AL = 0, CL =
t
;
CK
t
CK
=
=
t
CK(IDD)
t
CK(IDD)
I
DD
;
Measurement Conditions
HYB18T512161B2F–20/25
t
;
RAS
t
RAS
=
Symbol
I
I
I
I
I
I
I
I
I
I
I
I
Internet Data Sheet
DD0
DD1
DD2P
DD2N
DD2Q
DD3P(0)
DD3P(1)
DD3N
DD4R
DD4W
DD5B
DD5D
TABLE 31
Note
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