HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 27

• Manufacturer Part Number: HYB18T512161B2F-20/25
• Description: 512-Mbit x16 DDR2 SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1) V
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.The DQS / DQS, input reference
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
7) For each of the terms, if not already an integer, round to the next highest integer.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change
9) timing is referenced to Industrial standard definition
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
11) MIN (
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Parameter
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh command
period
Read preamble
Read postamble
Active bank A to Active bank B command period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
Write recovery time for write with Auto-
Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see
data sheet.
level is the crosspoint when in differential strobe mode;The input reference level for signals other than CK/CK, DQS / DQS is defined in
Chapter 5.3
the WR parameter stored in the MR.
during power-down, a specific procedure is required.
mis-match between DQS / DQS and associated DQ in any given cycle.
be greater than the minimum specification limits for
DDQ
,
t
V
CL
DD
,
t
CH
refer to
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
of this data sheet.
Chapter
1.
V
REF
V
stabilizes. During the period before
TT
. See
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
WR
t
t
t
t
t
t
t
CL
OIT
QH
QHS
REFI
RFC
RPRE
RPST
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
Chapter 5
and
t
CH
).
–20
Min.
0
t
—
—
—
105
0.9
0.40
10
7.5
0.35 x
0.40
14
t
7.5
2
10 – AL
2
t
200
for the reference load for timing measurements.
HP
WR
RFC
27
–
/
t
t
+10
CK
QHS
t
CK
V
Max.
12
—
380
7.8
3.9
—
1.1
0.60
—
—
—
0.60
—
—
—
—
—
—
—
t
REF
CK
512-Mbit Double-Data-Rate-Two SDRAM
refers to the application clock period. WR refers to
stabilizes, CKE = 0.2 x
–25
Min.
0
t
—
—
—
105
0.9
0.40
10
7.5
0.35 x
0.40
15
t
7.5
2
8 – AL
2
t
200
HP
WR
RFC
–
/
t
t
+10
CK
QHS
t
CK
HYB18T512161B2F–20/25
Max.
12
—
380
7.8
3.9
—
1.1
0.60
—
—
—
0.60
—
—
—
—
—
—
—
V
DDQ
Internet Data Sheet
is recognized as low.
Chapter 5
Unit Notes
ns
ps
μs
μs
ns
t
t
ns
ns
t
t
ns
t
ns
t
t
t
ns
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
2)3)4)5)6)
13)14)
13)15)
16)
12)
12)
14)17)
17)
18)
19)
20)
20)
of this
1)