HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 20

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HYB18T512161B2F-20/25

Manufacturer Part Number
HYB18T512161B2F-20/25
Description
512-Mbit x16 DDR2 SDRAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
1)
2)
3)
4) The value of
5) The value of
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Symbol
V
V
V
V
V
IN(dc)
ID(dc)
ID(ac)
IX(ac)
OX(ac)
V
V
V
indicates the voltage at which differential input signals must cross.
indicates the voltage at which differential input signals must cross.
IN(dc)
ID(dc)
ID(ac)
specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
specifies the input differential voltage
specifies the input differential voltage
Parameter
DC input signal voltage
DC differential input voltage
AC differential input voltage
AC differential cross point input voltage
AC differential cross point output voltage 0.5 ×
V
V
IX(ac)
OX(ac)
is expected to equal 0.5 ×
is expected to equal 0.5 ×
V
V
TR
TR
V
V
DDQ
DDQ
V
V
CP
of the transmitting device and
Differential DC and AC Input and Output Logic Levels Diagram
CP
of the transmitting device and
required for switching. The minimum value is equal to
required for switching. The minimum value is equal to
–0.3
Min.
0.25
0.5
0.5 ×
Differential DC and AC Input and Output Logic Levels
20
V
V
DDQ
DDQ
Single-ended AC Input Test Conditions Diagram
– 0.175
– 0.125
V
V
IX(ac)
OX(ac)
512-Mbit Double-Data-Rate-Two SDRAM
is expected to track variations in
Max.
V
V
V
0.5 ×
0.5 ×
is expected to track variations in
DDQ
DDQ
DDQ
+ 0.3
+ 0.6
+ 0.6
V
V
DDQ
DDQ
+ 0.175
+ 0.125
HYB18T512161B2F–20/25
V
V
IH(dc)
IH(ac)
Internet Data Sheet
V
Unit
V
V
V
TABLE 22
V
FIGURE 2
FIGURE 3
IL(dc)
IL(ac)
V
.
DDQ
V
.
DDQ
.
V
.
Notes
1)
2)
3)
4)
5)
IX(ac)
V
OX(ac)

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