HYB18T512161B2F-20/25 QIMONDA [Qimonda AG], HYB18T512161B2F-20/25 Datasheet - Page 19

• Manufacturer Part Number: HYB18T512161B2F-20/25
• Description: 512-Mbit x16 DDR2 SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

5.3
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at
1) Input waveform timing is referenced to the input signal crossing through the
2) The input signal minimum Slew Rate is to be maintained over the range from
3) AC timings are referenced with input waveforms switching from
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
Symbol
V
V
V
V
Symbol
V
V
SLEW
IH(dc)
IL(dc)
IH(ac)
IL(ac)
REF
SWING.MAX
V
transitions.
IL(ac).MAX
for falling edges as shown in
Parameter
DC input logic high
DC input low
AC input logic high
AC input low
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum Slew Rate
DC & AC Characteristics
Figure 2
V
REF
Min.
V
–0.3
V
—
REF
REF
V
.
IL(ac)
19
+ 0.125
+ 0.250
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS signals are internally disabled and
don’t care.
to
V
IH(ac)
V
V
on the positive transitions and
REF
IH(ac).MIN
level applied to the device under test.
Value
0.5 x
1.0
1.0
Single-ended AC Input Test Conditions
512-Mbit Double-Data-Rate-Two SDRAM
to
V
V
REF
DDQ
Max.
V
V
—
V
DDQ
REF
REF
for rising edges and the range from
– 0.125
– 0.250
+ 0.3
DC & AC Logic Input Levels
HYB18T512161B2F–20/25
V
IH(ac)
Internet Data Sheet
Unit
V
V
V / ns
to
V
IL(ac)
TABLE 20
TABLE 21
on the negative
Units
V
V
V
V
Notes
1)
1)
2)3)
V
REF
to