CY14E256L CYPRESS [Cypress Semiconductor], CY14E256L Datasheet - Page 9

• Manufacturer Part Number: CY14E256L
• Description: 256-Kbit (32K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 001-06968 Rev. *C
Switching Waveforms
Notes:
Software Controlled STORE/RECALL Cycle
Hardware STORE Cycle
10. The software sequence is clocked with CE controlled READs.
11. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
12. Read and Write cycles in progress before HSB are given this amount of time to complete.
13. t
14. HSB must remain HIGH during READ and WRITE cycles.
t
t
t
t
t
t
t
t
t
t
Parameter
RC
AS
CW
GLAX
RECALL
STORE
DELAY
RESTORE
HLHX
HLBL
DQ (DATA OUT)
Parameter
RESTORE
ADDRESS
[12]
[6]
is only applicable after t
[13]
STORE/RECALL Initiation Cycle Time
Address Set-Up Time
Clock Pulse Width
Address Hold Time
RECALL Duration
STORE Cycle Duration
Time allowed to complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
Hardware STORE Low to STORE Busy
STORE
Figure 6. SRAM Read Cycle #1: Address Controlled
is complete.
t
OH
Description
Description
t
AA
PRELIMINARY
[10,11]
t
RC
DATA VALID
Min.
25
20
20
0
25ns part
[4, 5, 14]
Max.
Min
15
20
1
CY14E256L
Min.
45
30
20
0
45ns part
Max
700
300
CY14E256L
10
Max.
20
Page 9 of 16
Unit
ms
µs
ns
ns
ns
Unit
µs
ns
ns
ns
ns
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