CY14E256L CYPRESS [Cypress Semiconductor], CY14E256L Datasheet - Page 3

• Manufacturer Part Number: CY14E256L
• Description: 256-Kbit (32K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 001-06968 Rev. *C
Device Operation
The CY14E256L nvSRAM is made up of two functional
components paired in the same physical cell. These are a
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell to SRAM
(the RECALL operation). This unique architecture allows all
cells to be stored and recalled in parallel. During the STORE
and RECALL operations SRAM READ and WRITE operations
are inhibited. The CY14E256L supports Infinite reads and
writes just like a typical SRAM. In addition, it provides Infinite
RECALL operations from the nonvolatile cells and up to
1 million STORE operations.
SRAM Read
The CY14E256L performs a READ cycle whenever CE and
OE are low while WE and HSB are high. The address specified
on pins A
be accessed. When the READ is initiated by an address
transition, the outputs will be valid after a delay of t
cycle #1). If the READ is initiated by CE or OE, the outputs will
be valid at t
The data outputs will repeatedly respond to address changes
within the t
any control input pins, and will remain valid until another
address change or until CE or OE is brought high, or WE or
HSB is brought low.
SRAM Write
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until either
CE or WE goes high at the end of the cycle. The data on the
common I/O pins I/O
valid t
the end of an CE controlled WRITE. It is recommended that
OE be kept high during the entire WRITE cycle to avoid data
bus contention on common I/O lines. If OE is left low, internal
circuitry will turn off the output buffers t
low.
AutoStore Operation
The CY14E256L stores data to nvSRAM using one of three
storage operations. These three operations are Hardware
Store, activated by HSB, Software Store, activated by an
address sequence, and AutoStore, on device power down.
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14E256L.
During normal operation, the device will draw current from V
to charge a capacitor connected to the V
charge will be used by the chip to perform a single STORE
operation. If the voltage on the V
the part will automatically disconnect the V
SD
before the end of a WE controlled WRITE or before
0–14
AA
ACE
access time without the need for transitions on
determines which of the 32,768 data bytes will
or at t
0–7
DOE
will be written into the memory if it is
, whichever is later (READ cycle #2).
CC
pin drops below V
HZWE
CAP
CAP
pin. This stored
after WE goes
pin from V
PRELIMINARY
AA
SWITCH
(READ
CC
CC
,
.
A STORE operation will be initiated with power provided by the
V
Figure 1 shows the proper connection of the storage capacitor
(V
teristics table for the size of V
is driven to 5V by a charge pump internal to the chip. A pull-up
should be placed on WE to hold it inactive during power-up.
CAP
CAP
capacitor.
) for automatic store operation. Refer to the DC Charac-
Figure 2. System Power Mode
Figure 1. AutoStore
CAP
. The voltage on the V
®
Mode
CY14E256L
Page 3 of 16
CAP
pin
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