CY14E256L CYPRESS [Cypress Semiconductor], CY14E256L Datasheet - Page 5

• Manufacturer Part Number: CY14E256L
• Description: 256-Kbit (32K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 001-06968 Rev. *C
The software sequence may be clocked with CE-controlled
READs or OE-controlled READs. Once the sixth address in
the sequence has been entered, the STORE cycle will
commence and the chip will be disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence,
although it is not necessary that OE be low for the sequence
to be valid. After the t
SRAM will again be activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE-controlled
READ operations must be performed:
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is
transferred into the SRAM cells. After the t
the SRAM will once again be ready for READ and WRITE
operations. The RECALL operation in no way alters the data
in the nonvolatile elements.
Data Protection
The CY14E256L protects data from corruption during
low-voltage conditions by inhibiting all externally initiated
STORE and WRITE operations. The low voltage condition is
detected when V
WRITE mode (both CE and WE low) at power-up, after a
RECALL, or after a STORE, the WRITE will be inhibited until
a negative transition on CE or WE is detected. This protects
against inadvertent writes during power-up or brown-out
conditions.
Noise Considerations
The CY14E256L is a high-speed memory and so must have a
high-frequency bypass capacitor of approximately 0.1 µF
connected between V
are as short as possible. As with all high-speed CMOS ICs,
careful routing of power, ground, and signals will reduce circuit
noise.
Low Average Active Power
CMOS technology provides the CY14E256L the benefit of
drawing significantly less current when it is cycled at times
longer than 50 ns. Figure 4 shows the relationship between
Table 1. Hardware Mode Selection
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
CE
H
X
L
L
CC
< V
CC
STORE
WE
and V
SWITCH
H
X
L
X
cycle time has been fulfilled, the
SS
. If the CY14E256L is in a
, using leads and traces that
HSB
H
H
H
L
RECALL
PRELIMINARY
cycle time
A13–A0
X
X
X
X
I
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5V, 100% duty cycle
on chip enable).Only standby current is drawn when the chip
is disabled. The overall average current drawn by the
CY14E256L depends on the following items:
Preventing STOREs
The STORE function can be disabled on the fly by holding HSB
high with a driver capable of sourcing 30 mA at a V
least 2.2V, as it will have to overpower the internal pull-down
device that drives HSB low for 20 µs at the onset of a STORE.
When the CY14E256L is connected for AutoStore operation
(system V
V
CY14E256L will attempt to pull HSB low; if HSB doesn’t
actually get below V
and abort the STORE attempt.
1. The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. CMOS vs. TTL Input Levels.
5. The operating temperature.
6. The V
7. I/O loading.
CC
CAP
and READ/WRITE cycle time. Worst-case current
) and V
Nonvolatile STORE
Not Selected
Figure 5. Current vs. Cycle Time (WRITE)
Read SRAM
Write SRAM
Figure 4. Current vs. Cycle Time (READ)
CC
CC
Mode
level.
CC
connected to V
crosses V
IL
,the part will stop trying to pull HSB low
Output High-Z
Output High-Z
SWITCH
Output Data
Input Data
CC
I/O
and a 68-µF capacitor on
on the way down, the
CY14E256L
Page 5 of 16
Standby
Power
Active
Active
I
CC2
OH
of at
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