CY14E256L CYPRESS [Cypress Semiconductor], CY14E256L Datasheet - Page 4

• Manufacturer Part Number: CY14E256L
• Description: 256-Kbit (32K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 001-06968 Rev. *C
In system power mode (Figure 2), both V
connected to the +5V power supply without the 68-µF
capacitor. In this mode the AutoStore function of the
CY14E256L will operate on the stored system charge as
power goes down. The user must, however, guarantee that
V
If an automatic STORE on power loss is not required, then V
can be tied to ground and + 5V applied to V
is the AutoStore Inhibit mode, in which the AutoStore function
is disabled. If the CY14E256L is operated in this configuration,
references to V
data sheet. In this mode, STORE operations may be triggered
through software control or the HSB pin. It is not permissible
to change between these three options “on the fly”.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent
STORE or RECALL cycle. Software initiated STORE cycles
are performed regardless of whether a WRITE operation has
taken place. The HSB signal can be monitored by the system
to detect an AutoStore cycle is in progress. (In the above
Figures 1, 2 and 3 * indicates that If HSB is not used, it should
be left unconnected.)
Hardware STORE (HSB) Operation
The CY14E256L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin can be
used to request a hardware STORE cycle. When the HSB pin
is driven low, the CY14E256L will conditionally initiate a
STORE operation after t
only begin if a WRITE to the SRAM took place since the last
STORE or RECALL cycle. The HSB pin also acts as an
open-drain driver that is internally driven low to indicate a busy
condition while the STORE (initiated by any means) is in
progress.
SRAM READ and WRITE operations that are in progress
when HSB is driven low by any means are given time to
complete before the STORE operation is initiated. After HSB
goes low, the CY14E256L will continue SRAM operations for
CC
does not drop below 3.6V during the 10-ms STORE cycle.
Figure 3. AutoStore Inhibit Mode
CC
should be changed to V
DELAY
. An actual STORE cycle will
CAP
CAP
CC
(Figure 3). This
throughout this
and V
PRELIMINARY
CAP
are
CC
t
take place. If a WRITE is in progress when HSB is pulled low
it will be allowed a time, t
SRAM WRITE cycles requested after HSB goes low will be
inhibited until HSB returns high.
The HSB pin can be used to synchronize multiple CY14E256L
while using a single larger capacitor. To operate in this mode
the HSB pin should be connected together to the HSB pins
from the other CY14E256L. An external pull-up resistor to +5V
is required since HSB acts as an open-drain pull-down. The
V
together and share a single capacitor. The capacitor size must
be scaled by the number of devices connected to it. When any
one of the CY14E256L detects a power loss and asserts HSB,
the common HSB pin will cause all parts to request a STORE
cycle (a STORE will take place in those CY14E256L that have
been written since the last nonvolatile cycle).
During any STORE operation, regardless of how it was
initiated, the CY14E256L will continue to drive the HSB pin
low, releasing it only when the STORE is complete. Upon
completion of the STORE operation the CY14E256L will
remain disabled until the HSB pin returns high.
If HSB is not used, it should be left unconnected.
Hardware RECALL (Power-up)
During power-up, or after any low-power condition (V
V
V
RECALL cycle will automatically be initiated and will take
t
If the CY14E256L is in a WRITE state at the end of power-up
RECALL, the SRAM data will be corrupted. To help avoid this
situation, a 10-Kohm resistor should be connected either
between WE and system V
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The CY14E256L
software STORE cycle is initiated by executing sequential
CE-controlled READ cycles from six specific address locations
in exact order. During the STORE cycle an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the cycle is
completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence, or the
sequence will be aborted and no STORE or RECALL will take
place.
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
DELAY
HRECALL
CAP
SWITCH
CC
once again exceeds the sense voltage of V
. During t
pins from the other CY14E256L parts can be tied
), an internal RECALL request will be latched. When
to complete.
DELAY
, multiple SRAM READ operations may
CC
DELAY
or between CE and system V
, to complete. However, any
CY14E256L
Page 4 of 16
SWITCH
CC
CC
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