NAND08GW3C2A NUMONYX [Numonyx B.V], NAND08GW3C2A Datasheet - Page 17

• Manufacturer Part Number: NAND08GW3C2A
• Description: 8/16 Gbit, 2112 byte page, 3 V supply, multilevel, multiplane, NAND Flash memory
• Manufacturer: NUMONYX [Numonyx B.V]

NAND08GW3C2A, NAND16GW3C2A
4
4.1
4.2
4.3
4.4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section. See the summary in
Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
Command Input
Command Input bus operations are used to give commands to the memory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See
Address Input
Address Input bus operations are used to input the memory addresses. Five bus cycles are
required to input the addresses (refer to
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See
Data Input
Data Input bus operations are used to input the data to be programmed. Data is only
accepted when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable
is Low and Read Enable is High. The data is latched on the rising edge of the Write Enable
signal. The data is input sequentially using the Write Enable signal.
See
Data Output
Data Output bus operations are used to read: the data in the memory array, the status
register, the electronic signature and the unique identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
If the Read Enable pulse frequency is lower then 33 MHz (t
output data is latched on the rising edge of Read Enable signal (see
Figure 16
Figure 17
Figure 18
and
and
and
Table 20
Table 20
Table 20
for details of the timings requirements.
for details of the timings requirements.
for details of the timing requirements.
Table 4: Bus
Table 5: Address
operations.
insertion).
RLRL
higher than 30 ns), the
Figure
Bus operations
19).
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