ST16C1450CJ28 EXAR [Exar Corporation], ST16C1450CJ28 Datasheet - Page 19

• Manufacturer Part Number: ST16C1450CJ28
• Description: 2.97V TO 5.5V UART
• Manufacturer: EXAR [Exar Corporation]

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REV. 4.2.0
MCR[2]: OP1# Output/Soft Reset
OP1# is not available as an output pin on the 145X. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
In normal operation, this bit is associated with the RST (buffered reset) output pin. The logical state of the RST
pin will follow exactly the logical state of the RESET pin. When IER bit-5 = 1, soft resets from MCR bit-2 are
ORed with the state of the RESET input pin. Therefore both reset types will be seen at the RST pin. Note that
asserting MCR bit-2 does not reset the 145X.
MCR[3]: OP2# or INT Output Enable
When not in Internal Loopback Mode:
OP2# is not available as an output pin on the 145X. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem CD# interface signal.
MCR[4]: Internal Loopback Enable
MCR[6:5]: Reserved
MCR[7]: Power Down Enable
This bit can only be accessed when IER bit-5 = 1.
This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic
1, an LSR interrupt will be generated when the character that is in the RHR has an error (parity, framing,
overrun, break).
LSR[0]: Receive Data Ready Indicator
LSR[1]: Receiver Overrun Error Flag
4.7
Logic 0 = OP1# output (RI# input) is at logic 1 (default).
Logic 1 = OP1# output (RI# input) is at logic 0.
Logic 0 = The RST output pin is a logic 0 (default).
Logic 1 = The RST output pin is a logic 1.
Logic 0 = INT output is three-state (default).
Logic 1 = INT output is active high.
Logic 0 = OP2# output (CD# input) is a logic 1 (default).
Logic 1 = OP2# output (CD# input) is a logic 0.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = Normal mode (default).
Logic 1 = Power down mode.
Logic 0 = No data in receive holding register (default).
Logic 1 = Data has been received and is saved in the receive holding register.
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while there is data in the RHR. In this case the previous data in the receive shift
register is overwritten. Note that under this condition the data byte in the receive shift register is not
transferred into the RHR, therefore the data in the RHR is not corrupted by the error.
Line Status Register (LSR) - Read Only
See “Power Down Mode” on page 11.
19
Figure
7.
2.97V TO 5.5V UART
ST16C1450/51