ST16C1450CJ28 EXAR [Exar Corporation], ST16C1450CJ28 Datasheet - Page 10

• Manufacturer Part Number: ST16C1450CJ28
• Description: 2.97V TO 5.5V UART
• Manufacturer: EXAR [Exar Corporation]

ST16C1450/51
2.97V TO 5.5V UART
The receiver section contains an 8-bit Receive Shift Register (RSR) and a byte-wide Receive Holding Register
(RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming character in
the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X clock rate. After 8 clocks the start bit period should be at the center of the start bit. At this
time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner
prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and
validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR
register bits 2-4. Upon unloading the receive data byte from RHR, the error tags are immediately updated to
reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon
receiving a characterThe RHR interrupt is enabled by IER bit-0.
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register.
It provides the receive data interface to the host processor. When there is data in the RHR register, the 3 error
tags in LSR register (bits 2-4) indicates if there are any errors associated with that byte.
2.5
2.5.1
Receiver
Receive Holding Register (RHR) - Read-Only
F
IGURE
16X Clock
5. T
Data
Byte
RANSMITTER
Transmit Shift Register (TSR)
O
PERATION
Transmit
Register
Holding
(THR)
10
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
S
B
TXNOFIFO1
L
S
B
áç
áç
áç
áç
REV. 4.2.0