ST16C1450CJ28 EXAR [Exar Corporation], ST16C1450CJ28 Datasheet - Page 16

• Manufacturer Part Number: ST16C1450CJ28
• Description: 2.97V TO 5.5V UART
• Manufacturer: EXAR [Exar Corporation]

ST16C1450/51
2.97V TO 5.5V UART
]
ISR[0]: Interrupt Status
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
ISR[7:4]: Reserved
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
4.5
4.4.1
4.4.2
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by received data in RHR.
TXRDY is by THR empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
LSR interrupt is cleared by a read to the LSR register (but flags and tags not cleared until character(s) that
generated the interrupt(s) has been emptied or cleared from RHR).
RXRDY interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register AND disabling the TXRDY interrupt (set IER bit-1 =
0), or by loading data into the TX FIFO.
MSR interrupt is cleared by a read to the MSR register.
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
P
RIORITY
Line Control Register (LCR) - Read/Write
1
2
3
4
-
Interrupt Generation:
Interrupt Clearing:
L
EVEL
B
IT
0
0
0
0
0
-3
ISR R
B
EGISTER
IT
1
1
0
0
0
T
-2
ABLE
4: I
S
B
TATUS
IT
1
0
1
0
0
NTERRUPT
-1
B
ITS
B
IT
0
0
0
0
1
-0
S
OURCE AND
16
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
None (default)
P
RIORITY
S
L
OURCE OF INTERRUPT
EVEL
áç
áç
áç
áç
REV. 4.2.0
Table
4).