ST16C1450CJ28 EXAR [Exar Corporation], ST16C1450CJ28 Datasheet
ST16C1450CJ28
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ST16C1450CJ28 Summary of contents
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OCTOBER 2003 GENERAL DESCRIPTION The ST16C1450, ST16C1451 series (here on denoted as the 145X universal asynchronous receiver and transmitter (UART). The 145X is foot print compatible to the SSI 73M1550 and SSI 73M2550 UART with one byte FIFO ...
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... PACKAGE 1 N.C. N. ST16C1450CQ48 CS# 9 N.C. 10 N.C. 11 N.C. 12 28-PLCC PACKAGES ST16C1450CJ28 CS OTE PINOUTS NOT TO SCALE ACTUAL SIZE OF TQFP PACKAGE IS SMALLER THAN PLCC PACKAGE 36 N.C. 35 N.C. 34 CTS# 33 RESET 32 DTR# 31 RTS N. ...
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REV. 4.2 ST16C1451 P IGURE INOUTS 48-TQFP PACKAGE 1 N. ST16C1451CQ48 CS# N.C. 10 N.C. 11 N.C. 12 28-PLCC ...
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... ST16C1450/51 2.97V TO 5.5V UART ORDERING INFORMATION ART UMBER ACKAGE ST16C1450CP28 28-Lead PDIP ST16C1450CJ28 28-Lead PLCC ST16C1450CQ48 48-Lead TQFP ST16C1451CP28 28-Lead PDIP ST16C1451CJ28 28-Lead PLCC ST16C1451CQ48 48-Lead TQFP ST16C1450IP28 28-Lead PDIP ST16C1450IJ28 28-Lead PLCC ST16C1450IQ48 48-Lead TQFP ST16C1451IP28 28-Lead PDIP ST16C1451IJ28 28-Lead PLCC ...
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REV. 4.2.0 PIN DESCRIPTIONS 28-P 28-P 28-P 28 PLCC PLCC N AME PDIP PDIP (1450) (1451) (1450) (1451) DATA BUS INTERFACE ...
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ST16C1450/51 2.97V TO 5.5V UART 28-P 28-P 28-P 28 PLCC PLCC N PDIP PDIP AME (1450) (1451) (1450) (1451) RTS CTS DTR DSR CD# 27 ...
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REV. 4.2.0 28-P 28-P 28-P 28 PLCC PLCC N PDIP PDIP AME (1450) (1451) (1450) (1451) GND N. Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. ...
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ST16C1450/51 2.97V TO 5.5V UART 2.2 Crystal Oscillator or External Clock The 145X includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to the Baud Rate Generators (BRG) in the UART. XTAL1 is the input ...
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REV. 4.2 ABLE YPICAL DATA RATES WITH A D IVISOR FOR O Data Rate UTPUT Clock (Decimal) 400 2304 2400 384 4800 192 9600 96 19.2k 48 38.4k 24 76.8k 12 153.6k 6 ...
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ST16C1450/51 2.97V TO 5.5V UART IGURE RANSMITTER Data Byte 16X Clock Transmit Shift Register (TSR) 2.5 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and a byte-wide Receive Holding Register (RHR). The RSR uses ...
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REV. 4.2 IGURE ECEIVER PERATION IN NON 16X Clock Error Receive Tags in Data Byte LSR bits and Errors 2.6 Special (Enhanced Feature) Mode The 145X supports the standard features of the ...
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ST16C1450/51 2.97V TO 5.5V UART IGURE NTERNAL OOPBACK Transmit Shift Register Receive Shift Register VCC TX MCR bit-4=1 RX VCC RTS# RTS# CTS# CTS# VCC DTR# DTR# DSR# DSR# OP1# RI# RI# OP2# CD# CD# 12 ...
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REV. 4.2.0 3.0 UART INTERNAL REGISTERS The 145X has a set of configuration registers selected by address lines A0, A1 and A2. The 16C450 compatible registers can be accessed when LCR[ and the baud ...
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ST16C1450/51 2.97V TO 5.5V UART . T 3: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit-7 0 ...
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REV. 4.2.0 4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 Receive Holding Register (RHR) - Read- Only See “Receiver” on page 10. 4.2 Transmit Holding Register (THR) - Write-Only See “Transmitter” on page 9. 4.3 Interrupt Enable Register (IER) ...
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ST16C1450/51 2.97V TO 5.5V UART 4.4.1 Interrupt Generation: LSR is by any of the LSR bits and 4. RXRDY is by received data in RHR. TXRDY is by THR empty. MSR is by any of the MSR ...
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REV. 4.2.0 LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT-1 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified ...
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ST16C1450/51 2.97V TO 5.5V UART LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. LCR[5] = logic 0, parity is not forced (default). LCR[5] = logic 1 and LCR[4] = ...
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REV. 4.2.0 MCR[2]: OP1# Output/Soft Reset OP1# is not available as an output pin on the 145X. But it is available for use during Internal Loopback Mode. In the Loopback Mode, this bit is used to ...
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ST16C1450/51 2.97V TO 5.5V UART LSR[2]: Receive Data Parity Error Tag Logic parity error (default). Logic 1 = Parity error. The received character in RHR does not have correct parity information and is suspect. This error is ...
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REV. 4.2.0 CTS# (active high, logical 1). Normally this bit is the compliment of the CTS# input. In the loopback mode, this bit is equivalent to bit-1 in the MCR register. The CTS# input may be ...
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ST16C1450/51 2.97V TO 5.5V UART ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA ( Thermal Resistance (48-TQFP) Thermal Resistance (28-PDIP) Thermal Resistance (28-PLCC) ELECTRICAL CHARACTERISTICS DC ELECTRICAL ...
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REV. 4.2.0 AC ELECTRICAL CHARACTERISTICS TA (-40 + FOR INDUSTRIAL GRADE PACKAGE S P YMBOL ARAMETER CLK Clock Pulse Duration OSC Oscillator/External Clock Frequency T Address Setup ...
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ST16C1450/51 2.97V TO 5.5V UART IGURE LOCK IMING CLK EXTERNAL CLOCK IGURE ODEM NPUT UTPUT IOW# Active IOW RTS# Change of state DTR# CD# CTS# DSR# INT IOR# IOR RI# ...
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REV. 4.2 IGURE ATA US EAD IMING A0- A2 Address T AS CS2# IOR# T RDV D0- IGURE ATA US RITE IMING A0- A2 ...
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ST16C1450/51 2.97V TO 5.5V UART F 12 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY (ISR bit-5) IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX ...
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REV. 4.2.0 PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
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ST16C1450/51 2.97V TO 5.5V UART PACKAGE DIMENSIONS (28 PIN PDIP) Note: The control dimension is the inch column SYMBOL INCHES MILLIMETERS MIN MAX MIN 0.160 ...
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REV. 4.2.0 PACKAGE DIMENSIONS (28 PIN PLCC) Note: The control dimension is the inch column SYMBOL INCHES MILLIMETERS MIN ...
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ST16C1450/51 2.97V TO 5.5V UART REVISION HISTORY Date Revision January 2003 Rev 4.0.0 Changed to single column format. Clarified that the TX interrupt is not MS Windows compatible. Clarified timing diagrams. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and ...
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TO 5.5VUART GENERAL DESCRIPTION................................................................................................. 1 F ..................................................................................................................................................... 1 EATURES A ............................................................................................................................................... 1 PPLICATIONS ............................................................................................................................................................. 1 IGURE LOCK IAGRAM F 2. ST16C1450 P ..................................................................................................................................................... 2 IGURE INOUTS F 3. ST16C1451 P ..................................................................................................................................................... ...
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ST16C1450/51 REV. 4.2 & I IGURE ECEIVE EADY NTERRUPT F 13 & I IGURE RANSMIT EADY NTERRUPT P D (48 ACKAGE IMENSIONS PIN TQFP P D (28 PDIP) ..........................................................................................................28 ACKAGE IMENSIONS PIN P D ...