SAK-TC1767-256F133HL INFINEON [Infineon Technologies AG], SAK-TC1767-256F133HL Datasheet - Page 8

• Manufacturer Part Number: SAK-TC1767-256F133HL
• Description: 32-Bit Single-Chip Microcontroller
• Manufacturer: INFINEON [Infineon Technologies AG]

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Data Sheet
High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Single precision Floating Point Unit (FPU)
– 133 MHz operation at full temperature range
32-bit Peripheral Control Processor with single cycle instruction (PCP2)
– 8 Kbyte Parameter Memory (PRAM)
– 16 Kbyte Code Memory (CMEM)
– 133 MHz operation at full temperature range
Multiple on-chip memories
– 72 Kbyte Data Memory (LDRAM)
– 24 Kbyte Code Scratchpad Memory (SPRAM)
– 2 Mbyte Program Flash Memory (PFlash)
– 64 Kbyte Data Flash Memory (DFlash, represents 16 Kbyte EEPROM)
– Instruction Cache: up to 8 Kbyte (ICACHE, configurable)
– Data Cache: up to 4 Kbyte (DCACHE, configurable)
– 8 Kbyte Overlay Memory (OVRAM)
– 16 Kbyte BootROM (BROM)
8-Channel DMA Controller
Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
High performing on-chip bus structure
– 64-bit Local Memory Buses between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (LFI Bridge)
Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
– Two High-Speed Synchronous Serial Channels (SSC) with programmable data
– One serial Micro Second Bus interface (MSC) for serial port expansion to external
– One High-Speed Micro Link interface (MLI) for serial inter-processor
– One MultiCAN Module with 2 CAN nodes and 64 free assignable message objects
– One General Purpose Timer Array Modules (GPTA) with additional Local Timer
32 analog input lines for ADC
parity, framing and overrun error detection
length and shift direction
power devices
communication
for high efficiency data handling via FIFO buffering and gateway data transfer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
Summary of Features
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Summary of Features
V1.3, 2009-09
TC1767