SAK-TC1767-256F133HL INFINEON [Infineon Technologies AG], SAK-TC1767-256F133HL Datasheet - Page 46

• Manufacturer Part Number: SAK-TC1767-256F133HL
• Description: 32-Bit Single-Chip Microcontroller
• Manufacturer: INFINEON [Infineon Technologies AG]

2.4.6.1
The General Purpose Timer Array (GPTA0) provides a set of hardware modules
required for high-speed digital signal processing:
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Input lines can be shared by an LTC and a GTC to trigger their programmed operation
simultaneously.
The following list summarizes the specific features of the GPTA units.
Clock Generation Unit
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Data Sheet
Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
Phase Discrimination Logic units (PDL) decode the direction information output by a
rotation tracking system.
Duty Cycle Measurement Cells (DCM) provide pulse-width measurement
capabilities.
A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA
module clock ticks during an input signal’s period.
Global Timer units (GT) driven by various clock sources are implemented to operate
as a time base for the associated Global Timer Cells.
Global Timer Cells (GTC) can be programmed to capture the contents of a Global
Timer on an external or internal event. A GTC may also be used to control an external
port pin depending on the result of an internal compare operation. GTCs can be
logically concatenated to provide a common external port pin with a complex signal
waveform.
Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs – enabled in Timer Mode or Capture Mode – can be clocked or
triggered by various external or internal events.
On-chip Trigger and Gating Signals (OTGS) can be configured to provide trigger or
gating signals to integrated peripherals.
Filter and Prescaler Cell (FPC)
– Six independent units
– Three basic operating modes:
– Selectable input sources:
– Selectable input clocks:
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Phase Discriminator Logic (PDL)
– Two independent units
– Two operating modes (2- and 3- sensor signals)
Prescaler, Delayed Debounce Filter, Immediate Debounce Filter
Port lines, GPTA module clock, FPC output of preceding FPC cell
GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or
uncompensated PLL clock.
f
GPTA
/2 maximum input signal frequency in Filter Modes
Functionality of GPTA0
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Introduction
V1.3, 2009-09
TC1767