SAK-TC1767-256F133HL INFINEON [Infineon Technologies AG], SAK-TC1767-256F133HL Datasheet - Page 54

• Manufacturer Part Number: SAK-TC1767-256F133HL
• Description: 32-Bit Single-Chip Microcontroller
• Manufacturer: INFINEON [Infineon Technologies AG]

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Additionally, in depth performance analysis and profiling support is provided by the
Emulation Device through MCDS Event Counters driven by a variety of trigger signals
(e.g. cache hit, wait state, interrupt accepted).
2.5.2
For detailed tracing of the system’s behavior a pin-compatible Emulation Device is
available.
2.5.3
Two main use cases are catered for by resources in addition the OCDS Level 1
infrastructure: Overlay of non-volatile on-chip memory and non-intrusive signaling:
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1) The OCDS L2 interface of AudoNG is not available.
Data Sheet
Different Boot modes to use application software not yet programmed to the Flash.
A total of four hardware breakpoints for the TriCore based on instruction address,
data address or combination of both.
Unlimited number of software breakpoints (DEBUG instruction) for TriCore and PCP.
Debug event generated by access to a specific address via the system peripheral
bus.
Tool access to all SFRs and internal memories independent of the Cores.
Two central Break Switches to collect debug events from all modules (TriCore, PCP,
DMA, BCU, break input pins) and distribute them selectively to breakable modules
(TriCore, PCP, break output pins).
Central Suspend Switch to suspend parts of the system (TriCore, PCP, Peripherals)
instead if breaking them as reaction to a debug event.
Dedicated interrupt resources to handle debug events inside TriCore (breakpoint
trap, software interrupt) and Cerberus (can trigger PCP), e.g. for implementing
Monitor programs.
Access to all OCDS Level 1 resources also for TriCore and PCP themselvesitself for
debug tools integrated into the application code.
Triggered Transfer of data in response to a debug event; if target is programmed to
be a device interface simple variable tracing can be done.
8 KB SRAM for Overlay.
Can be split into up to 16 blocks which can overlay independent regions of on-chip
Data Flash.
Changing the configuration is triggered by a single SFR access to maintain
consistency.
Overlay configuration switch does not require the TriCore to be stopped or
suspended.
1)
Real Time Trace
Calibration Support
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Introduction
V1.3, 2009-09
TC1767