AD9397/PCB AD [Analog Devices], AD9397/PCB Datasheet - Page 9

• Manufacturer Part Number: AD9397/PCB
• Description: DVI Display Interface
• Manufacturer: AD [Analog Devices]

Pin
DATA OUTPUTS
DATA CLOCK OUTPUT
POWER SUPPLY
GND
1
The supplies should be sequenced such that V
RED [7:0]
GREEN [7:0]
BLUE [7:0]
DATACK
V
V
D
DD
PV
DV
(3.3 V)
(1.8 V to 3.3 V)
DD
DD
(1.8 V)
(1.8 V)
1
Description
Data Output, Red Channel.
Data Output, Green Channel.
Data Output, Blue Channel.
The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed, but is
different if the color space converter is used. When the sampling time is changed by adjusting the phase
register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the
timing relationship among the signals is maintained.
Data Clock Output.
This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four
possible output clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2×
pixel clock, 1× pixel clock, 2× frequency pixel clock, and a 90° phase shifted pixel clock). They are
produced either by the internal PLL clock generator or EXTCLK and are synchronous with the pixel
sampling clock. The polarity of DATACK can also be inverted via Register 0x24 [0]. The sampling time of
the internal pixel clock can be changed by adjusting the phase register. When this is changed, the pixel-
related DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all moved, so the
timing relationship among the signals is maintained.
Analog Power Supply.
These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.
Digital Output Power Supply.
A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power
supply transients (noise). These supply pins are identified separately from the V
transferred into the sensitive analog circuitry can be minimized. If the AD9397 is interfacing with lower
voltage logic, V
Clock Generator Power Supply.
The most sensitive portion of the AD9397 is the clock generation circuitry. These pins provide power to
the clock PLL and help the user design for optimal performance. The designer should provide quiet,
noise-free power to these pins.
Digital Input Power Supply.
This supplies power to the digital logic.
Ground.
The ground return for all circuitry on chip. It is recommended that the AD9397 be assembled on a single
solid ground plane, with careful attention to ground current paths.
D
and V
DD
are never less than 300 mV below DV
DD
may be connected to a lower supply voltage (as low as 1.8 V) for compatibility.
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DD
. At no time should DV
DD
be more than 300 mV greater than V
D
pins, so output noise
AD9397
D
or V
DD
.