AD9397/PCB AD [Analog Devices], AD9397/PCB Datasheet - Page 21

• Manufacturer Part Number: AD9397/PCB
• Description: DVI Display Interface
• Manufacturer: AD [Analog Devices]

0x30—Bit[6] DVI Content Encrypted
This read-only bit is high when HDCP decryption is in use
(content is protected). The signal goes low when HDCP is not
being used. Customers can use this bit to allow copying of the
content. The bit should be sampled at regular intervals because
it can change on a frame-by-frame basis. 0 = HDCP not in use.
1 = HDCP decryption in use.
0x30—Bit[5] DVI HSYNC Polarity
This read-only bit indicates the polarity of the DVI HSYNC. 0 =
DVI HSYNC polarity is low active. 1 = DVI HSYNC polarity is
high active.
0x30—Bit[4] DVI VSYNC Polarity
This read-only bit indicates the polarity of the DVI VSYNC.
0 = DVI VSYNC polarity is low active. 1 = DVI VSYNC polarity
is high active.
MACROVISION
0x31—Bits[7:4] Macrovision Pulse Max
These bits set the pseudo sync pulse width maximum for
Macrovision detection in pixel clocks. This is functional for
13.5 MHz SDTV or 27 MHz progressive scan. Power-up
default is 9.
0x31—Bits[3:0] Macrovision Pulse Min
These bits set the pseudo sync pulse width maximum for
Macrovision detection in pixel clocks. This is functional for
13.5 MHz SDTV or 27 MHz progressive scan. Power up
default is 6.
0x32—Bit[7] Macrovision Oversample Enable
Tells the Macrovision detection engine whether oversampling
is used. This accommodates 27 MHz sampling for SDTV and
54 MHz sampling for progressive scan and is used as a
correction factor for clock counts. Power-up default is 0.
0x32—Bit[6] Macrovision PAL Enable
Tells the Macrovision detection engine to enter PAL mode when
set to 1. Default is 0 for NTSC mode.
0x32—Bits[5:0] Macrovision Line Count Start
Set the start line for Macrovision detection. Along with
Register 0x33, Bits [5:0], they define the region where MV
pulses are expected to occur. The power-up default is Line 13.
0x33—Bit[7] Macrovision Detect Mode
0 = standard definition. 1 = progressive scan mode
0x33—Bit[6] Macrovision Settings Override
This defines whether preset values are used for the MV line
counts and pulse widths or the values stored in I
used. 0 = use hard-coded settings for line counts and pulse
widths. 1 = use I
2
C values for these settings.
2
C registers are
Rev. 0 | Page 21 of 28
0x33—Bits[5:0] Macrovision Line Count End
Set the end line for Macrovision detection. Along with Register
0x32, Bits [5:0], they define the region where MV pulses are
expected to occur. The power-up default is Line 21.
0x34—Bits[7:6] Macrovision Pulse Limit Select
Set the number of pulses required in the last three lines (SD
mode only). If there is not at least this number of MV pulses,
the engine stops. These two bits define these pulse counts:
0x34—Bit[5] Low Frequency Mode
Sets whether the audio PLL is in low frequency mode or not.
Low frequency mode should only be set for pixel clocks
<80 MHz.
0x34—Bit[4] Low Frequency Override
Allows the previous bit to be used to set low frequency mode
rather than the internal autodetect.
0x34—Bit[3] Upconversion Mode
0 = repeat Cb/Cr values. 1 = interpolate Cb/Cr values.
0x34—Bit[2] CbCr Filter Enable
Enables the FIR filter for 4:2:2 CbCr output.
COLOR SPACE CONVERSION
The default power-up values for the color space converter
coefficients (R0x35 through R0x4C) are set for ATSC RGB-to-
YCbCr conversion. They are completely programmable for
other conversions.
0x34—Bit[1] Color Space Converter Enable
This bit enables the color space converter. 0 = disable color
space converter. 1 = enable color space converter. The power-up
default setting is 0.
0x35—Bits[6:5] Color Space Converter Mode
These two bits set the fixed-point position of the CSC
coefficients, including the A4, B4, and C4 offsets. Default = 01.
Table 14. CSC Fixed Point Converter Mode
Select
00
01
1×
00 = 6.
01 = 4.
10 = 5 (default).
11 = 7.
Result
±1.0, −4096 to +4095
±2.0, −8192 to +8190
±4.0, −16384 to +16380
AD9397