AD9397/PCB AD [Analog Devices], AD9397/PCB Datasheet - Page 12

• Manufacturer Part Number: AD9397/PCB
• Description: DVI Display Interface
• Manufacturer: AD [Analog Devices]

AD9397
4:4:4 TO 4:2:2 FILTER
The AD9397 contains a filter that allows it to convert a signal
from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the
maximum accuracy and fidelity of the original signal.
Input Color Space to Output Color Space
The AD9397 can support a wide variety of output formats,
such as:
•
•
•
•
Color Space Conversion (CSC) Matrix
The CSC matrix in the AD9397 consists of three identical
processing channels. In each channel, three input values are
multiplied by three separate coefficients. Also included are an
offset value for each row of the matrix and a scaling multiple
for all values. Each value has a 13-bit, twos complement
resolution to ensure the signal integrity is maintained. The
CSC is designed to run at speeds up to 150 MHz supporting
resolutions up to 1080p at 60 Hz. With any-to-any color space
support, formats such as RGB, YUV, YCbCr, and others are
supported by the CSC.
The main inputs, R
inputs from each channel. These inputs are based on the input
format detailed in Table 9. The mapping of these inputs to the
CSC inputs is shown in Table 8.
Table 8. CSC Port Mapping
Input Channel
R/CR
Gr/Y
B/CB
Table 9.
Port
Bit
4:4:4
4:2:2
4:4:4 DDR
4:2:2 to 12
1
Arrows in the table indicate clock edge. Rising edge of clock = ↑, falling edge = ↓.
RGB 24-bit
4:4:4 YCrCb 8-bit
4:2:2 YCrCb 8-bit, 10-bit, and 12-bit
Dual 4:2:2 YCrCb 8-bit
Red
7
Red/Cr [7:0]
CbCr [7:0]
DDR
DDR
CbCr[11:0]
IN
, G
↑
↓
6
1
R [7:0]
IN
G [3:0]
, and B
5
4
IN
CSC Input Channel
R
G
B
, come from the 8-bit to 12-bit
IN
IN
B
IN
3
DDR
↑
2
B [7:4]
1
0
Green
7
Green/Y [7:0]
Y [7:0]
DDR
DDR
Rev. 0 | Page 12 of 28
↑
↓
6
B [3:0]
G [7:4]
5
4
G
One of the three channels is represented in Figure 6. In each
processing channel, the three inputs are multiplied by three
separate coefficients marked a1, a2, and a3. These coefficients
are divided by 4096 to obtain nominal values ranging from
–0.9998 to +0.9998. The variable labeled a4 is used as an offset
control. The CSC_Mode setting is the same for all three
processing channels. This multiplies all coefficients and offsets
by a factor of 2
The functional diagram for a single channel of the CSC, as
shown in Figure 6, is repeated for the remaining G and B
channels. The coefficients for these channels are b1, b2, b3, b4,
c1, c2, c3, and c4.
R
B
A programming example and register settings for several
common conversions are listed in the Color Space Converter
(CSC) Common Settings section.
For a detailed functional description and more programming
examples, refer to the Application Note
Space Converter User's Guide.
OUTPUT DATA FORMATS
The AD9398 supports 4:4:4, 4:2:2, double data-rate (DDR), and
BT656 output formats. Register 0x25[3:0] controls the output
mode. These modes and the pin mapping are illustrated in
Table 8.
IN
IN
IN
[11:0]
[11:0]
[11:0]
3
DDR 4:2:2
DDR 4:2:2
Y [11:0]
a2[12:0]
a3[12:0]
a1[12:0]
2
×
×
×
CSC_Mode
↑
↓
1
CbCr [11:0]
Y,Y [11:0]
×
×
×
4096
4096
4096
Figure 6. Single CSC Channel
1
0
1
1
.
Blue
7
Blue/Cb [7:0]
DDR 4:2:2
+
6
+
↑
5
a4[12:0]
CbCr
+
AN-795, AD9880 Color
4
↓
Y, Y
×4
×2
3
CSC_Mode[1:0]
2
2
1
0
R
OUT
1
[11:0]
0