AD9397/PCB AD [Analog Devices], AD9397/PCB Datasheet - Page 8

• Manufacturer Part Number: AD9397/PCB
• Description: DVI Display Interface
• Manufacturer: AD [Analog Devices]

AD9397
Pin Type
POWER SUPPLY
CONTROL
HDCP
DATA ENABLE
RTERM
Table 6. Pin Function Descriptions
Pin
INPUTS
OUTPUTS
SERIAL PORT
Rx0+
Rx0−
Rx1+
Rx1−
Rx2+
Rx2−
RxC+
RxC−
PWRDN
RTERM
HSOUT
VSOUT
FIELD
DE
CTL(3-0)
SDA
SCL
DDCSDA
DDCSCL
MDA
MCL
Pin No.
80, 76, 72, 67,
45, 33
100, 90, 10
59, 56, 54
48, 32, 30
83
82
49
50
51
52
88
46
Description
Digital Input Channel 0 True.
Digital Input Channel 0 Complement.
Digital Input Channel 1 True.
Digital Input Channel 1 Complement.
Digital Input Channel 2 True.
Digital input Channel 2 Complement.
These six pins receive three pairs of transition minimized differential signaling (TMDS ) pixel data
(at 10× the pixel rate) from a digital graphics transmitter.
Digital Data Clock True.
Digital Data Clock Complement.
This clock pair receives a TMDS clock at 1× pixel data rate.
Power-Down Control/Three-State Control.
The function of this pin is programmable via Register 0x26 [2:1].
RTERM is the termination resistor used to drive the AD9397 internally to a precise 50 Ω termination for
TMDS lines. This should be a 500 Ω 1% tolerance resistor.
Horizontal Sync Output.
A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this
output can be programmed via serial bus registers. By maintaining alignment with DATACK and Data,
data timing with respect to horizontal sync can always be determined.
Vertical Sync Output.
The separated VSYNC from a composite signal or a direct pass through of the VSYNC signal. The polarity
of this output can be controlled via the serial bus bit (Register 0x24 [6]).
Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced
signal) is odd or even. The polarity of this signal is programmable via Register 0x24[4].
Data Enable that defines valid video. Can be received in the signal or generated by the AD9397.
Control 3, Control 2, Control 1, and Control 0 are output from the DVI stream. Refer to the DVI 1.0
specification for explanation.
Serial Port Data I/O for Programming AD9397 Registers—I
Serial Port Data Clock for Programming AD9397 Registers.
Serial Port Data I/O for HDCP Communications to Transmitter—I
Serial Port Data Clock for HDCP Communications to Transmitter.
Serial Port Data I/O to EEPROM with HDCP Keys—I
Serial Port Data Clock to EEPROM with HDCP Keys.
Mnemonic
V
V
PV
DV
GND
SDA
SCL
DDCSCL
DDCSDA
MCL
MDA
DE
RTERM
D
DD
DD
DD
Rev. 0 | Page 8 of 28
Function
Analog Power Supply and DVI Terminators
Output Power Supply
PLL Power Supply
Digital Logic Power Supply
Ground
Serial Port Data I/O
Serial Port Data Clock
HDCP Slave Serial Port Data Clock
HDCP Slave Serial Port Data I/O
HDCP Master Serial Port Data Clock
HDCP Master Serial Port Data I/O
Data Enable
Sets Internal Termination Resistance
2
C Address is 0xA0.
2
C Address is 0x98.
2
C Address is 0x74 or 0x76.
Value
1.8 V to 3.3 V
1.8 V
1.8 V
0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V
3.3 V CMOS
500 Ω