AD9397/PCB AD [Analog Devices], AD9397/PCB Datasheet - Page 14

• Manufacturer Part Number: AD9397/PCB
• Description: DVI Display Interface
• Manufacturer: AD [Analog Devices]

AD9397
Hex
Address
0x25
0x26
0x27
Read/Write
or Read Only
Read/Write
Read/Write
Read/Write
Bits
[4]
[0]
[7
[5:4]
[3:2]
[1]
[0]
[7]
[5]
[4]
[3]
[2:1]
[0]
[7
[6]
[5]
[4]
[3]
[2:0]
:6]
]
Default
Value
*
*
0
*
*
*
*******0
0*******
**0*****
***0****
****1***
*
*
1
*
*
***0****
****0***
*****000
**1****
******0
*11****
***00**
*****1*
****00*
******0
0******
*0*****
1******
*******
Register Name
F
O
O
O
Strength
O
P
Enable
Seconda
Enable
Output Thr
SPDIF Three-State
I
Power-Down Pin
Polarity
P
Function
P
A
Enable
H
M
Enable
BT656 EN
Force DE Generation
Interlace Offset
2
ield Output Polarity
rimary Output
S Three-State
ower-Down Pin
ower-Down
uto Power-Down
utput CLK Invert
utput CLK Select
utput Drive
utput Mode
DCP A0
CLK External
ry Output
Rev. 0 | Page 14 of 28
ee-State
Description
O
0 = active low out.
1 = active high out.
0 = Don’t invert clock
1 = Invert clock out.
Selects which clock to
down from TMDS clock input when pixel repetition is in use.
00 = ½× CLK.
01 = 1× CLK.
10 = 2× CLK.
11 = 90° phase 1× CLK.
Sets the drive strength o
00 = lowest, 11 = highest.
Selects which pins the data
00 = 4:4:4 mode (normal).
01 = 4:2:2 + DDR 4:2:2 on blue.
10 = DDR 4:4:4 + DDR 4:2:2 on blue.
Enables primary output.
Enables secondary output (DDR 4:2:2 in Output Mode 1 and
Mode 2).
Three-stat
Three-state the SPDIF output.
Three-state the I
Sets polarity of power-down pin.
0 = active low.
1 = active high.
Selects the function of the po
00 = power-down.
01 = power-down and three-state SOG.
10 = three-state outputs only.
11 = three-state outputs and SOG.
0 = normal.
1 = power-down.
0 = disable auto lo
1 = enable auto low power state.
Sets the LSB of the address of the
second receiver in a dual-link configuration.
0 = use internally generated MCLK.
1 = use external MCLK input.
If an external MCLK is used, it
according to the CTS and N available in the I
between the internal MCLK and the input MCLK results in
dropped or repeated audio samples.
Enables EAV/SAV codes to be inserted
data.
Allows
Sets the difference (in HSYNCs) in field length betwee
and Field 1.
utput field polarity.
use of the internal DE generator in DVI mode.
e the outputs.
2
S output and the MCLK out.
w power state.
out.
use on output pin. 1× CLK is divided
f the outputs.
comes out on.
wer-down pin.
must be locked to the video clock
HDCP I
into the video output
2
C. Set to 1 only for a
2
C. Any mismatch
n Field 0