AN983 ETC [List of Unclassifed Manufacturers], AN983 Datasheet - Page 42

• Manufacturer Part Number: AN983
• Description: PCI/miniPCI-to-Ethernet LAN Controller
• Manufacturer: ETC [List of Unclassifed Manufacturers]

CSR19 (offset = 8ch) - PCIC, PCI bus performance counter
RO* = Read only and cleared by reading.
CSR20 (offset = 90h) - PMCSR, Power Management Command and Status
(The same register value mapping to CR49-PMR1.)
6
5
4
3~2
1
0
Bit #
31~16
15~8
7~0
Bit #
31~16
15
Rev. 1.8
RWP
PAUSE
RTE
DRT
SINT
ATUR
Name
CLKCNT
---
DWCNT
Name
---
PMES
0: de-assert pmez signal
Reset Wake-up Pattern Data Register Pointer
0: Normal
1: Reset
PAUSE function control to disable or enable the PAUSE
function for flow control. The default value of PAUSE is
decided by the result of Auto-Negotiation. Driver can force
to enable or disable it after the Auto-Negotiation completed.
0: PAUSE function is disabled.
1: PAUSE function is enabled
Receive Threshold Enable.
1: the receive FIFO threshold is enabled.
0: disable the receive FIFO threshold selection in bit 3~2 of
this register, the receive threshold is set to 64-byte.
Drain Receive Threshold
00: 32 bytes (8 DW)
01: 64 bytes (16 DW)
10: store-and -forward
11: reserved
Software interrupt.
1: enable automatically transmit-underrun recovery.
Descriptions
The number of PCI clock from read request asserted to
access completed. This PCI clock number is accumulated all
the read command cycles from last CSR19 read to current
CSR19 read.
Reserved
The number of double word accessed by the last bus master.
This double word number is accumulated all the bus master
data transactions from last CSR19 read to current CSR19
read.
Descriptions
Reserved
PME_Status, This bit is set when the AN983B would normally
assert the PME# signal for wakeup event, this bit is
independent of the state of the PME-En bit.
Writing a “1” to this bit will clear it and cause the AN983B to
stop asserting a PME#(if enabled). Writing a “0” has no
AN983B
www.admtek.com.tw
ADMtek Inc.
PCI/miPCI Fast Ethernet Controller with integrated PHY
0
0
0
01
0
0
Default Val RW Type
0
0
Default Val RW Type
0
RO*
RO*
RO
R/W
R/W
R/W
R/W
R/W
R/W
42