AN983 ETC [List of Unclassifed Manufacturers], AN983 Datasheet - Page 34

• Manufacturer Part Number: AN983
• Description: PCI/miniPCI-to-Ethernet LAN Controller
• Manufacturer: ETC [List of Unclassifed Manufacturers]

W* = only write when the transmit processor stopped.
W** = only write when the transmit and receive processor both stopped.
W*** = only write when the receive processor stopped.
CSR7 (offset = 38h), IER - Interrupt Enable Register
2
1
0
Bit #
31~17
16
15
14
13
12
11
10
9
8
7
6
Rev. 1.8
---
SR
---
Name
---
NIE
AIE
---
FBEIE
GPTIE
RWTIE
RSIE
RUIE
RCIE
0: filters all bad packets
Reserved
Start/Stop Receive
0: receive processor will enter stop state after the
current reception frame completed. This value is
effective only when the receive processor is in the
running or suspending state. Notice: In “Stop
Receive” state, the PAUSE packet and Remote Wake
Up packet won’t be affected and can be received if
the corresponding function is enabled.
1: receive processor will enter running state.
Reserved
Descriptions (Refer to CSR5)
Reserved
Normal Interru
1: enable all the normal interrupt bits (see bit16 of CSR5)
Abnormal Interrupt Enable
1: enable all the abnormal interrupt bits (see bit 15 of
CSR5)
Reserved
Fatal Bus Error Interrupt Enable
1: combine this bit and bit 15 of CSR7 to enable fatal
bus error interrupt
General Purpose Timer Interrupt Enable
1: combine this bit and bit 15 of CSR7 to enable
general-purpose timer expired interrupt.
Receive Watchdog Time-out Interrupt Enable
1: combine this bit and bit 15 of CSR7 to enable
receive watchdog time-out interrupt.
Receive Stopped Interrupt Enable
1: combine this bit and bit 15 of CSR7 to enable
receive stopped interrupt.
Recei
1: combine this bit and bit 15 of CSR7 to enable
receive descriptor unavailable interrupt.
Receive Completed Interrupt Enable
ve Descriptor Unavailable Interrupt Enable
AN983B
pt Enable
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ADMtek Inc.
PCI/miPCI Fast Ethernet Controller with integrated PHY
0
Default Val RW Type
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
34