AN983 ETC [List of Unclassifed Manufacturers], AN983 Datasheet - Page 29

• Manufacturer Part Number: AN983
• Description: PCI/miniPCI-to-Ethernet LAN Controller
• Manufacturer: ETC [List of Unclassifed Manufacturers]

7.2.2. CONTROL/STATUS REGISTER DESCRIPTION
CSR0 (offset = 00h), PAR - PCI Access Register
Bit #
31~25
24
23
22
21
20~19
18,17
16
15, 14
13 ~ 8
7
Rev. 1.8
Name
---
MWIE
MRLE
---
MRME
---
TAP
---
CAL
PBL
BLE
Descriptions
Reserved
Memory Write and Invalidate Enable.
1: enable AN983B to generate memory write invalidate
command. AN983B will generate this command while writing
full cache lines.
0: disable AN983B to generate memory write invalidate
command and use memory write commands instead.
Memory Read Line Enable.
1: enable AN983B to generate memory read line command,
while read access instruction reach the cache line boundary.
If the read access instruction doesn’t reach the cache line
boundary then AN983B uses the memory read command
instead.
Reserved
Memory Read Multiple Enable.
1: enable AN983B to generate memory read multiple
commands while reading full cache line. If the memory is not
cache aligned, the AN983B uses memory read command
instead.
Reserved
Transmit auto-polling in transmit suspended state,
00: disable auto-polling (default)
01: polling own-bit every 200 us
10: polling own-bit every 800 us
11: polling own-bit every 1600 us
Reserved
Cache alignment, address boundary for data burst, set after
reset
00: reserved (default)
01: 8 DW boundary alignment
10: 16 DW boundary alignment
11: 32 DW boundary alignment
Programmable Burst Length. This value defines the maximum
number of DW to be transferred in one DMA transaction.
Value: 0 (unlimited), 1, 2, 4, 8, 16(default), 32
Big or Little Endian selection.
0: little endian (e.g. INTEL)
1: big endian (only for data buffer)
AN983B
www.admtek.com.tw
ADMtek Inc.
PCI/miPCI Fast Ethernet Controller with integrated PHY
Default Val RW Type
0
0
0
00
00
010000
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
29