MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 202

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MC68HC908QY2

Manufacturer Part Number
MC68HC908QY2
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet

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Break Module (BREAK)
17.3 Features
17.4 Functional Description
202
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
Features of the break module include:
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the system integration module (SIM). The SIM then causes the CPU
to load the instruction register with a software interrupt instruction (SWI)
after completion of the current CPU instruction. The program counter
vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
When a CPU generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the microcontroller unit
(MCU) to normal operation.
module.
Figure 17-2
Accessible input/output (I/O) registers during the break Interrupt
Central processor unit (CPU) generated break interrupts
Software-generated break interrupts
Computer operating properly (COP) disabling during break
interrupts
A CPU generated address (the address in the program counter)
matches the contents of the break address registers.
Software writes a logic 1 to the BRKA bit in the break status and
control register.
provides a summary of the I/O registers.
Break Module (BREAK)
Figure 17-1
shows the structure of the break
MOTOROLA

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