MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 365

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908AS60 — Rev. 1.0
MOTOROLA
TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response
Control Bits
These three bits control the type of in-frame response being sent. The
programmer should not set more than one of these control bits to a 1
at any given time. However, if more than one of these three control
bits are set to 1, the priority encoding logic will force these register bits
to a known value as shown in
written to TSIFR, TMIFR1, and TMIFR0, then internally they will be
encoded as 010. However, when these bits are read back, they will
read 011.
The BDLC supports the in-frame response (IFR) feature of J1850 by
setting these bits correctly. The four types of J1850 IFR are shown in
the following figure. The purpose of the in-frame response modes is
to allow multiple nodes to acknowledge receipt of the data by
responding with their personal ID or physical address in a
concatenated manner after they have seen the EOD symbol. If
transmission arbitration is lost by a node while sending its response,
it continues to transmit its ID/address until observing its unique byte
in the response stream. For VPW modulation, the first bit of the IFR is
always passive; therefore, an active normalization bit must be
generated by the responder and sent prior to its ID/address byte.
When there are multiple responders on the J1850 bus, only one
normalization bit is sent which assists all other transmitting nodes to
sync their responses.
Freescale Semiconductor, Inc.
Write/Read
For More Information On This Product,
TSIFR
Byte Data Link Controller-Digital (BDLC-D)
0
1
0
0
Table 21-4. BDLC Transmit In-Frame Response
Go to: www.freescale.com
Write/Read
TMIFR1
Control Bit Priority Encoding
0
X
1
0
Write/Read
TMIFR0
Table
X
X
0
1
Byte Data Link Controller-Digital (BDLC-D)
21-4. For example, if 011 is
Actual
TSIFR
0
1
0
0
TMIFR1
Actual
BDLC CPU Interface
0
0
1
0
Technical Data
TMIFR0
Actual
0
0
0
1
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