MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 361

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908AS60 — Rev. 1.0
MOTOROLA
IE— Interrupt Enable Bit
WCM — Wait Clock Mode Bit
This bit determines whether the BDLC will generate CPU interrupt
requests in run mode. It does not affect CPU interrupt requests when
exiting the BDLC stop or BDLC wait modes. Interrupt requests will be
maintained until all of the interrupt request sources are cleared by
performing the specified actions upon the BDLC’s registers. Interrupts
that were pending at the time that this bit is cleared may be lost.
If the programmer does not wish to use the interrupt capability of the
BDLC, the BDLC state vector register (BSVR) can be polled
periodically by the programmer to determine BDLC states. See
BDLC State Vector Register
This bit determines the operation of the BDLC during CPU wait mode.
See
use.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 =
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
Byte Data Link Controller-Digital (BDLC-D)
21.8.2 Stop Mode
Frequency
1.049 MHz
2.097 MHz
4.194 MHz
8.389 MHz
1.000 MHz
2.000 MHz
4.000 MHz
8.000 MHz
f
XCLK
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Table 21-3. BDLC Rate Selection
R1
0
0
1
1
0
0
1
1
and
21.8.1 Wait Mode
for a description of the BSVR.
R0
Byte Data Link Controller-Digital (BDLC-D)
0
1
0
1
0
1
0
1
Division
1
2
4
8
1
2
4
8
for more details on its
BDLC CPU Interface
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
f
BDLC
Technical Data
21.7.4
361