MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 295

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

19.7 TIM During Break Interrupts
19.8 I/O Registers
MC68HC908AS60 — Rev. 1.0
MOTOROLA
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See
Register.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
These I/O registers control and monitor operation of the TIM:
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Freescale Semiconductor, Inc.
For More Information On This Product,
TIM status and control register (TSC)
TIM counter registers (TCNTH–TCNTL)
TIM counter modulo registers (TMODH–TMODL)
Go to: www.freescale.com
Modulo Timer (TIM)
9.8.3 SIM Break Flag Control
TIM During Break Interrupts
Modulo Timer (TIM)
Technical Data
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