PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 94

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2682/2685/4682/4685
FIGURE 5-8:
DS39761B-page 92
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
the SFRs, or locations F60h to
0FFh (Bank 15) of data
memory.
Locations below 60h are not
available in this addressing
mode.
When a = 0 and f ≤ 5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When a = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
Preliminary
FFFh
FFFh
FFFh
F00h
F60h
F00h
F60h
000h
060h
080h
100h
F00h
F60h
000h
080h
100h
000h
080h
100h
Data Memory
Data Memory
Data Memory
Bank 14
Bank 15
Bank 15
Bank 14
Bank 15
Bank 14
through
Bank 0
Bank 1
Bank 0
through
through
Bank 1
Bank 0
Bank 1
SFRs
SFRs
SFRs
00000000
001001da
001001da
BSR
Access RAM
FSR2H
© 2007 Microchip Technology Inc.
ffffffff
ffffffff
FSR2L
00h
60h
FFh
Valid Range
for ‘f’