PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 478

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2682/2685/4682/4685
T
T0CON Register
Table Reads/Table Writes .................................................. 64
TBLRD ............................................................................. 401
TBLWT ............................................................................. 402
Time-out in Various Situations (table) ................................ 45
Timer0 .............................................................................. 147
Timer1 .............................................................................. 151
Timer2 .............................................................................. 157
Timer3 .............................................................................. 159
Timing Diagrams
DS39761B-page 476
PSA Bit ..................................................................... 149
T0CS Bit ................................................................... 148
T0PS2:T0PS0 Bits ................................................... 149
T0SE Bit ................................................................... 148
Associated Registers ............................................... 149
Clock Source Edge Select (T0SE Bit) ...................... 148
Clock Source Select (T0CS Bit) ............................... 148
Operation ................................................................. 148
Overflow Interrupt .................................................... 149
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 148
16-Bit Read/Write Mode ........................................... 153
Associated Registers ............................................... 155
Interrupt .................................................................... 154
Operation ................................................................. 152
Oscillator .................................................................. 153
Resetting, Using a Special Event
Special Event Trigger (ECCP1) ............................... 174
Use as a Real-Time Clock ....................................... 154
Associated Registers ............................................... 158
Interrupt .................................................................... 158
Operation ................................................................. 157
Output ...................................................................... 158
PR2 Register .................................................... 169, 175
TMR2 to PR2 Match Interrupt .................................. 169
16-Bit Read/Write Mode ........................................... 161
Associated Registers ............................................... 161
Operation ................................................................. 160
Oscillator .................................................. 151, 159, 161
Overflow Interrupt .................................................... 161
Special Event Trigger (ECCP1) ............................... 161
TMR3H Register .............................................. 151, 159
TMR3L Register ............................................... 151, 159
A/D Conversion ........................................................ 452
Acknowledge Sequence .......................................... 220
Asynchronous Reception ......................................... 239
Asynchronous Transmission .................................... 237
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 235
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 240
Baud Rate Generator with Clock Arbitration ............ 214
BRG Overflow Sequence ......................................... 235
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 438
Bus Collision During a Repeated
Bus Collision During a Repeated
Layout Considerations ..................................... 154
Trigger Output (CCP1) ..................................... 154
(Back-to-Back) ................................................. 237
Normal Operation ............................................. 240
During Start Condition ...................................... 223
Start Condition (Case 1) .................................. 224
Start Condition (Case 2) .................................. 224
Preliminary
Bus Collision During a Start Condition
Bus Collision During a Start Condition
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision for Transmit and
Capture/Compare/PWM (All CCP Modules) ............ 440
CLKO and I/O .......................................................... 437
Clock Synchronization ............................................. 207
Clock/Instruction Cycle .............................................. 65
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 442
Example SPI Master Mode (CKE = 1) ..................... 443
Example SPI Slave Mode (CKE = 0) ....................... 444
Example SPI Slave Mode (CKE = 1) ....................... 445
External Clock (All Modes Except PLL) ................... 435
Fail-Safe Clock Monitor ........................................... 357
First Start Bit Timing ................................................ 215
Full-Bridge PWM Output .......................................... 179
Half-Bridge PWM Output ......................................... 178
High/Low-Voltage Detect Characteristics ................ 432
High-Voltage Detect (VDIRMAG = 1) ...................... 270
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect (VDIRMAG = 0) ....................... 269
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4682/4685) ................... 441
Parallel Slave Port (PSP) Read ............................... 145
Parallel Slave Port (PSP) Write ............................... 145
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 181
PWM Direction Change at Near
PWM Output ............................................................ 169
Repeated Start Condition ........................................ 216
Reset, Watchdog Timer (WDT), Oscillator
Send Break Character Sequence ............................ 241
Slave Synchronization ............................................. 193
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 192
SPI Mode (Slave Mode with CKE = 0) ..................... 194
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 446
C Bus Start/Stop Bits ............................................ 446
C Master Mode (7 or 10-Bit Transmission) ........... 218
C Master Mode (7-Bit Reception) .......................... 219
C Slave Mode (10-Bit Reception, SEN = 0) .......... 204
C Slave Mode (10-Bit Reception, SEN = 1) .......... 209
C Slave Mode (10-Bit Transmission) .................... 205
C Slave Mode (7-Bit Reception, SEN = 0) ............ 202
C Slave Mode (7-Bit Reception, SEN = 1) ............ 208
C Slave Mode (7-Bit Transmission) ...................... 203
C Slave Mode General Call Address
(SCL = 0) ......................................................... 223
(SDA Only) ...................................................... 222
(Case 1) ........................................................... 225
(Case 2) ........................................................... 225
Acknowledge ................................................... 221
(Master/Slave) ................................................. 450
(Master/Slave) ................................................. 450
Sequence (7 or 10-Bit Address Mode) ............ 210
Auto-Restart Disabled) .................................... 184
Auto-Restart Enabled) ..................................... 184
100% Duty Cycle ............................................. 181
Start-up Timer (OST) and Power-up
Timer (PWRT) ................................................. 438
V
DD
Rise > T
2
2
C Bus Data ........................................ 448
C Bus Start/Stop Bits ........................ 448
PWRT
© 2007 Microchip Technology Inc.
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DD
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