PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 38

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2682/2685/4682/4685
If the IRCF bits were previously at a non-zero value or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
FIGURE 3-3:
FIGURE 3-4:
DS39761B-page 36
INTRC
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Note 1: T
Multiplexer
CPU Clock
PLL Clock
Peripheral
Program
INTOSC
Counter
Output
OSC1
Clock
Q1
SCS1:SCS0 bits Changed
OST
Q2
PC
TRANSITION TIMING TO RC_RUN MODE
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
= 1024 T
Q3
Q4
OSC
Q1
; T
Q1
PLL
1
T
OST
= 2 ms (approx). These intervals are not shown to scale.
(1)
PC
2
Q2
Clock Transition
3
T
PLL
OSTS bit Set
Q3
Preliminary
(1)
PC + 2
n-1
Q4
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
n
Q1
1
Transition
2
Clock
n-1 n
Q2
PC + 2
Q3
Q2
Q4
© 2007 Microchip Technology Inc.
Q3 Q4
Q1
Q1
Q2
PC + 4
PC + 4
Q2
Q3
Q3