PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 253
![no-image](/images/no-image-200.jpg)
PIC18F2682-I/PT
Manufacturer Part Number
PIC18F2682-I/PT
Description
28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2682-IPT.pdf
(484 pages)
- Current page: 253 of 484
- Download datasheet (9Mb)
The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The ADRESH/ADRESL
registers will contain unknown data after a Power-on
Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine acquisition time, see Section 19.1 “A/D
Acquisition Requirements”. After this acquisition
time has elapsed, the A/D conversion can be started.
An acquisition time can be programmed to occur
between setting the GO/DONE bit and the actual start
of the conversion.
FIGURE 19-2:
© 2007 Microchip Technology Inc.
Legend: C
V
AIN
Rs
V
I
R
SS
C
R
LEAKAGE
T
ANALOG INPUT MODEL
PIN
IC
HOLD
SS
ANx
C
5 pF
PIN
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
various junctions
V
DD
PIC18F2682/2685/4682/4685
V
V
T
T
= 0.6V
= 0.6V
Preliminary
I
± 500 nA
LEAKAGE
The following steps should be followed to perform an
A/D conversion:
1.
2.
3.
4.
5.
6.
7.
R
IC
Configure the A/D module:
• Configure analog pins, voltage reference and
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time (if required).
Start conversion:
• Set GO/DONE bit (ADCON0 register)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as T
required before next acquisition starts.
≤ 1k
digital I/O (ADCON1)
V
SS
DD
Sampling
Switch
6V
5V
4V
3V
2V
AD
R
SS
. A minimum wait of 2 T
Sampling Switch
5 6 7 8 9 10 11
V
SS
C
HOLD
DS39761B-page 251
= 120 pF
(kΩ)
AD
is
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