PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 154

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2682/2685/4682/4685
12.1
Timer1 can operate in one of these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
FIGURE 12-1:
FIGURE 12-2:
DS39761B-page 152
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T13CKI
T1OSO/T13CKI
Timer1 Operation
T1OSI
T1OSI
Timer1 Oscillator
Timer1 Oscillator
TIMER1 BLOCK DIAGRAM
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1OSCEN
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
T1OSCEN
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
(1)
(1)
TMR1CS
TMR1CS
(CCP1 Special Event Trigger)
Clear TMR1
Clear TMR1
(CCP1 Special Event Trigger)
Clock
Internal
F
F
Internal
Clock
OSC
OSC
/4
/4
Preliminary
On/Off
1
0
1
0
Prescaler
Prescaler
1, 2, 4, 8
cycle (Fosc/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and RC0/
T1OSO/T13CKI pins become inputs. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
1, 2, 4, 8
2
2
TMR1L
TMR1L
8
8
Synchronize
Synchronize
Sleep Input
Sleep Input
High Byte
TMR1H
Detect
Detect
TMR1
8
High Byte
TMR1
© 2007 Microchip Technology Inc.
8
8
Set
TMR1IF
on Overflow
Read TMR1L
Write TMR1L
Internal Data Bus
1
0
1
0
Set
TMR1IF
on Overflow
Timer1
On/Off
Timer1
On/Off