FDC37B80X SMSC [SMSC Corporation], FDC37B80X Datasheet - Page 73

• Manufacturer Part Number: FDC37B80X
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

Bit 1
Delta Data Set Ready (DDSR). Bit 1 indicates
that the nDSR input has changed state since the
last time the MSR was read.
Bit 2
Trailing Edge of Ring Indicator (TERI). Bit 2
indicates that the nRI input has changed from
logic "0" to logic "1".
Bit 3
Delta Data Carrier Detect (DDCD).
indicates that the nDCD input to the chip has
changed state.
Note: Whenever bit 0, 1, 2, or 3 is set to a logic
"1", a MODEM Status Interrupt is generated.
Bit 4
This bit is the complement of the Clear To Send
(nCTS) input. If bit 4 of the MCR is set to logic
"1", this bit is equivalent to nRTS in the MCR.
Bit 5
This bit is the complement of the Data Set
Ready (nDSR) input. If bit 4 of the MCR is set
to logic "1", this bit is equivalent to DTR in the
MCR.
Bit 6
This bit is the complement of the Ring Indicator
(nRI) input. If bit 4 of the MCR is set to logic
"1", this bit is equivalent to OUT1 in the MCR.
Bit 7
This bit is the complement of the Data Carrier
Detect (nDCD) input. If bit 4 of the MCR is set
to logic "1", this bit is equivalent to OUT2 in the
MCR.
SCRATCHPAD REGISTER (SCR)
Address Offset =7H, DLAB =X, READ/WRITE
This 8 bit read/write register has no effect on the
operation of the Serial Port. It is intended as a
scratchpad
programmer to hold data temporarily.
register
to
be
used
by
Bit 3
the
73
PROGRAMMABLE BAUD RATE GENERATOR
(AND DIVISOR LATCHES DLH, DLL)
The Serial Port contains a programmable Baud
Rate Generator that is capable of taking any
clock input (DC to 3 MHz) and dividing it by any
divisor from 1 to 65535. This output frequency
of the Baud Rate Generator is 16x the Baud
rate. Two 8 bit latches store the divisor in 16 bit
binary format. These Divisor Latches must be
loaded during initialization in order to insure
desired operation of the Baud Rate Generator.
Upon loading either of the Divisor Latches, a 16
bit Baud counter is immediately loaded. This
prevents long counts on initial load. If a 0 is
loaded into the BRG registers the output divides
the clock by the number 3. If a 1 is loaded the
output is the inverse of the input oscillator. If a
two is loaded the output is a divide by 2 signal
with a 50% duty cycle.
loaded the output is low for 2 bits and high for
the remainder of the count. The input clock to
the BRG is a 1.8462 MHz clock.
Table 31 shows the baud rates possible with a
1.8462 MHz crystal.
Effect Of The Reset on Register File
The Reset Function Table (Table 32) details the
effect of the Reset input on each of the registers
of the Serial Port.
FIFO INTERRUPT MODE OPERATION
When the RCVR FIFO and receiver interrupts
are enabled (FCR bit 0 = "1", IER bit 0 = "1"),
RCVR interrupts occur as follows:
A. The receive data available interrupt will be
B. The IIR receive data available indication also
issued when the FIFO has reached its
programmed trigger level; it is cleared as
soon
programmed trigger level.
occurs when the FIFO trigger level is
reached. It is cleared when the FIFO drops
below the trigger level.
as
the
FIFO
If a 3 or greater is
drops
below
its