FDC37B80X SMSC [SMSC Corporation], FDC37B80X Datasheet - Page 152

• Manufacturer Part Number: FDC37B80X
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

PME Status
Default = 0x00 on
POR V
PME Wake Status
Default = 0x00 on
V
TR
POR
NAME
TR
Table 64 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
(R/w Clear)
(R/w Clear)
INDEX
0xC6
0xC7
REG
Bit[0] PME_Status
= 0 (default)
= 1 Set when FDC37B80x would normally assert the
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT
RESET or HARD RESET.
Writing a “1” to PME_Status will clear it and cause
the FDC37B80x to stop asserting nPME, in enabled.
Writing a “0” to PME_Status has no effect.
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] Reserved
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[7:5] Reserved
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[4:0] will clear it. Writing a “0” to
any bit in PME Wake Status Register has no effect.
PCI nPME signal, independent of the state of the
PME_En bit.
152
DEFINITION
STATE