FDC37B80X SMSC [SMSC Corporation], FDC37B80X Datasheet - Page 134
FDC37B80X
Manufacturer Part Number
FDC37B80X
Description
PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.FDC37B80X.pdf
(194 pages)
- Current page: 134 of 194
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Chip Level (Global) Control/Configuration
Registers[0x00-0x2F]
The chip-level (global) registers lie in the
address range [0x00-0x2F]. The design MUST
use all 8 bits of the ADDRESS Port for register
selection. All unimplemented registers and bits
Config Control
Default = 0x00
on Vcc POR or
Reset_Drv
Index Address
Default = 0x03
on Vcc POR or
Reset_Drv
Logical Device #
Default = 0x00
on Vcc POR or
Reset_Drv
REGISTER
0x04 - 0x06 Reserved - Writes are ignored, reads return 0.
ADDRESS
0x03 R/W
0x07 R/W
0x02 W
0x00 -
0x01
Chip (Global) Control Registers
Table 53 - Chip Level Registers
Reserved - Writes are ignored, reads return 0.
The hardware automatically clears this bit after the
write, there is no need for software to clear the bits.
Bit 0 = 1: Soft Reset. Refer to the "Configuration
Registers" table for the soft reset value for each
register.
Bit[7]
= 1
= 0
Bits [6:2]
Reserved - Writes are ignored, reads return 0.
Bits[1:0]
Sets GP index register address when in Run mode
(not in Configuration Mode).
= 11
= 10
= 01
= 00
A write to this register selects the current logical
device.
configuration registers for each logical device.
Note: The Activate command operates only on the
selected logical device.
0xEA (Default)
0xE4
0xE2
0xE0
Enable WDT_CTRL and SMI Enable and
SMI Status Register access when not in
configuration mode
Disable WDT_CTRL and SMI Enable and
SMI Status Register access when not in
configuration mode (Default)
This allows access to the control and
134
ignore writes and return zero when read.
The INDEX PORT is used to select a
configuration register in the chip.
PORT is then used to access the selected
register. These registers are accessible only in
the Configuration Mode.
DESCRIPTION
The DATA
STATE
C
C
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