FDC37B80X SMSC [SMSC Corporation], FDC37B80X Datasheet - Page 149

• Manufacturer Part Number: FDC37B80X
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

SMI Enable
Register 1
Default = 0x00
on Vcc POR
KRST_GA20
Default = 0x00
on Vcc POR or
Reset_Drv
NAME
NAME
Table 64 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
Table 63 - KYBD, Logical Device 7 [Logical Device Number = 0x07]
0xF1 -
0xFF
REG INDEX
0xB4 R/W
INDEX
0xF0
R/W
REG
KRESET and GateA20 Select
Bit[7] Polarity Select for P12
Bits[6:3] Reserved
Bit[2] Port 92 Select
Bit[1] Reserved
Bit[0] Reserved
Reserved - read as ‘0’
This register is used to enable the different interrupt
sources onto the group nSMI output.
1=Enable
0=Disable
Bit[0] Reserved
Bit[1] EN_PINT
Bit[2] EN_U2INT
Bit[3] EN_U1INT
Bit[4] EN_FINT
Bit[5] Reserved
Bit[6] Reserved
Bit[7] EN_WDT
= 0 P12 active low (default)
= 1 P12 active high
= 0 Port 92 Disabled
= 1 Port 92 Enabled
149
DEFINITION
DEFINITION
STATE
STATE
C