PEB2085 SIEMENS [Siemens Semiconductor Group], PEB2085 Datasheet - Page 184

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PEB2085

Manufacturer Part Number
PEB2085
Description
ISDN SubscribernAccess Controller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet

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3.4
The control of the data transfer phase is mainly done by commands from the P to ISAC-S via
the Command Register (CMDR).
Table 16 gives a summary of possible interrupts from the HDLC controller and the appropriate
reaction to these interrupts.
Table 17 lists the most important commands which are issued by a microprocessor by setting
one or several bits in CMDR.
The powerful FIFO logic, which consists of a 2 32 byte receive and 2 32 byte transmit FIFO,
as well as an intelligent FIFO controller, builds a flexible interface to the upper protocol layers
implemented in the microcontroller.
The extent of LAPD protocol support is dependent on the selected message transfer mode,
see section 2.4.2.
Table 16
Interrupts from ISAC
Mnemonic Register
RPF
RME
RFO
PCE
Semiconductor Group
Control of Layer-2 Data Transfer
(addr. hex)
ISTA
ISTA
EXIR (24)
EXIR (24)
(20)
(20)
®
-S HDLC Controller
Meaning
Receive Pool Full. Request to
read received bytes of an
uncompleted HDLC frame from
RFIFO
Receive Message End. Request
to read received bytes of a
complete HDLC frame (or the
last part of a frame) from RFIFO.
Receive Frame Overflow. A
complete frame has been lost
because storage space in
RFIFO was not available.
Protocol Error. S or I-frame with
incorrect N(R) or S frame with
I-field received (in auto mode
only) or an I-frame which is not a
command or
S-frame with an undefined
control field.
Layer-2 Receive
184
Reaction
Read 32 bytes from RFIFO and
acknowledge with RMC.
Read RFIFO (number of bytes
given by RBCL4-0) and status
information and acknowledge
with RMC.
Error report for statistical
purposes. Possible cause:
deficiency in software.
Link re-establishment.
Indication to layer 3.
Operational Description

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