USB3300_06 SMSC [SMSC Corporation], USB3300_06 Datasheet - Page 40

• Manufacturer Part Number: USB3300_06
• Description: Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.06 (07-19-06)
6.2.3
6.3
6.4
SIGNALING MODE
OTG device, Peripheral Chirp
OTG device, Peripheral HS
OTG device, Peripheral FS
OTG device, Peripheral HS/FS Suspend
OTG device, Peripheral HS/FS Resume
OTG device, Peripheral Test J/Test K
Note: This is the same as Table 40, Section 4.4 of the ULPI 1.1 specification.
Bias Generator
This block consists of an internal bandgap reference circuit used for generating the driver current and
the biasing of the analog circuits. This block requires an external 12KΩ, 1% tolerance, external
reference resistor connected from RBIAS to ground.
The USB3300 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference
clock that is used by the PHY during both transmit and receive. The USB3300 requires a clean 24MHz
crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY
may not operate correctly.
The USB3300 can use either a crystal or an external clock oscillator for the 24MHz reference. The
crystal is connected to the XI and XO pins as shown in the application diagram,
oscillator is used the clock should be connected to the XI input and the XO pin left floating. When a
external clock is used the XI pin is designed to be driven with a 0 to 3.3 volt signal. When using an
external clock the user needs to take care to ensure the external clock source is clean enough to not
corrupt the high speed eye performance.
Once the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz
clock. The USB3300 is guaranteed to start the clock within the time specified in
USB3300 does not support using an external 60MHz clock input.
For Host Applications the USB3300 implements the ULPI AutoResume bit in the Interface Control
register. The default AutoResume state is 0 and this bit should be enabled for Host applications. For
more details please see sections 7.1.77 and 7.9 of the USB specification.
The USB3300 includes an integrated set of built in power management functions, including a POR
generator. Internal regulators enable the USB3300 to be powered from a single 3.3 volt power supply,
thereby reducing the bill of materials and simplifying product design.
Crystal Oscillator and PLL
Internal Regulators and POR
Table 6.8 DP/DM termination vs. Signaling Mode (continued)
00b
01b
00b
01b
01b
00b
DATASHEET
REGISTER SETTINGS
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
1b
0b
1b
1b
1b
0b
40
10b
00b
00b
00b
10b
10b
0b
0b
0b
0b
0b
0b
1b
1b
1b
1b
1b
1b
1b
0b
1b
1b
1b
0b
RESISTOR SETTINGS
0b
0b
0b
0b
0b
0b
Figure
0b
0b
0b
0b
0b
0b
Table
SMSC USB3300
7.1. If a clock
1b
1b
1b
1b
1b
1b
Datasheet
5.2. The
0b
1b
0b
0b
0b
1b