USB3300_06 SMSC [SMSC Corporation], USB3300_06 Datasheet - Page 29

• Manufacturer Part Number: USB3300_06
• Description: Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
• Manufacturer: SMSC [SMSC Corporation]

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
Datasheet
SMSC USB3300
6.1.5.1
COMMAND NAME
Register Read
Register Write
ULPI Register
DATA[7:0]
ULPI Register Write
A ULPI register write operation is given in
DATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the
TXD CMD byte.
To write to a register, the Link will wait until DIR is low, and at T0, drive the TXD CMD on the databus.
At T2 the PHY will drive NXT high. On the next rising clock edge, T3, the Link will write the register
data. At T4 the PHY will accept the register data and the Link will drive an Idle on the bus and drive
STP high to signal the end of the data packet. Finally, at T5, the PHY will latch the data into the register
and drive NXT low. The Link will pull STP low.
NXT is used to control when the Link drives the register data on the bus. DIR is low throughout this
transaction since the PHY is receiving data from the Link. STP is used to end the transaction and data
is registered after the de-assertion of STP. After the write operation completes, the Link must drive a
ULPI Idle (00h) on the data bus or the USB3300 may decode the bus value as a ULPI command.
CLK
STP
NXT
DIR
BITS[7:6]
Idle
CMD
10b
11b
Table 6.4 ULPI TXD CMD Byte Encoding (continued)
T0
Figure 6.4 ULPI Register Write
CMD BITS[5:0]
XXXXXXb
XXXXXXb
T1
(reg write)
TXD CMD
DATASHEET
Reg Data [n-1]
T2
29
Immediate Register Write Command where
DATA[5:0] = 6-bit register address
Immediate Register Read Command where
DATA[5:0] = 6-bit register address
Figure
T3
6.4. The TXD command with a register write
Reg Data[n]
COMMAND DESCRIPTION
T4
Idle
T5
Reg Data [n]
Revision 1.06 (07-19-06)
T6