USB3300_06 SMSC [SMSC Corporation], USB3300_06 Datasheet - Page 19

• Manufacturer Part Number: USB3300_06
• Description: Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
• Manufacturer: SMSC [SMSC Corporation]

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
Datasheet
Chapter 6 Architecture Overview
SMSC USB3300
6.1
6.1.1
VDD3.3
CLKOUT
DATA[7:0]
STP
NXT
DIR
The USB3300 architecture can be broken down into the following blocks shown in
The USB3300 uses the industry standard ULPI digital interface to facilitate communication between
the PHY and Link (device controller). The ULPI interface is designed to reduce the number of pins
required to connect a discrete USB PHY to an ASIC or digital controller. For example, a full UTMI+
Level 3 OTG interface requires 54 signals while a ULPI interface requires only 12 signals.
The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI)
Specification” document (www.ulpi.org). The following sections highlight the key operating modes
of the USB3300 digital interface.
Overview
Figure 6.2
does not use a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies.
ULPI Digital
Regulator &
ULPI Digital
illustrates the block diagram of the ULPI digital functions. It should be noted that this PHY
Internal
POR
Figure 6.1 Simplified USB3300 Architecture
DATASHEET
USB3300
HS XCVR
XTAL &
FS/LS
XCVR
19
PLL
Resistors
Module
Gen.
Bias
OTG
Revision 1.06 (07-19-06)
Figure 6.1
VDD3.3
RBIAS
VBUS
DM
DP
ID
below.