USB3300_06 SMSC [SMSC Corporation], USB3300_06 Datasheet - Page 22

• Manufacturer Part Number: USB3300_06
• Description: Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.06 (07-19-06)
6.1.3
6.1.4
Setup time (control in, 8-bit data in)
Hold time (control in, 8-bit data in)
Output delay (control out, 8-bit data out)
Control Out -
Clock Out -
Control In -
DATA[7:0]
DATA[7:0]
Data Out -
DIR, NXT
CLKOUT
Data In -
STP
ULPI Interface Timing
The control and data timing relationships are given in
provides CLKOUT and all timing is relative to the rising clock edge. The timing relationships detailed
below apply to Synchronous Mode only.
Note: V
ULPI Register Array
The USB3300 PHY implements all of the ULPI registers detailed in the ULPI revision 1.1 specification.
The complete USB3300 ULPI register set is shown in
includes the default states of the register upon POR. The RESET bit in the Function Control Register
does not reset the bits of the ULPI register array. The Link should not read or write to any registers
not listed in this table.
PARAMETER
DD3.3
T
T
SD
SC
= 3.0 to 3.6V; V
T
HC
T
Figure 6.3 ULPI Timing Diagram
Table 6.2 ULPI Interface Timing
HD
SS
= 0V; T
DATASHEET
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface
A
SYMBOL
T
T
22
T
HC
DC
= -40C to 85C; unless otherwise specified.
SC
, T
, T
,T
SD
HD
DD
T
T
DD
Table
DC
Figure 6.3
6.3. All registers are 8 bits. This table also
MIN
5.0
2.0
0
and
Table
6.2. The USB300 PHY
MAX
5.0
T
DC
SMSC USB3300
Datasheet
UNITS
ns
ns
ns