PIC18F2220 MICROCHIP [Microchip Technology], PIC18F2220 Datasheet - Page 45

• Manufacturer Part Number: PIC18F2220
• Description: 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

4.0
The PIC18F2X20/4X20 devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
FIGURE 4-1:
 2003 Microchip Technology Inc.
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
MCLR
OSC1
Power-on Reset (POR)
MCLR Reset while executing instructions
MCLR Reset when not executing instructions
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
V
DD
RESET
2: See Table 4-1 for time-out situations.
Instruction
RESET
OST/PWRT
INTRC
Pointer
Stack
32 s
( )_IDLE
Brown-out
Time-out
V
Detect
Sleep
DD
WDT
(1)
Reset
Rise
OST
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
PWRT
Stack Full/Underflow Reset
External Reset
10-bit Ripple Counter
MCLRE
11-bit Ripple Counter
POR Pulse
BOREN
1024 Cycles
65.5 ms
PIC18F2220/2320/4220/4320
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 4-2. These bits
are used in software to determine the nature of the
Reset. See Table 4-3 for a full description of the Reset
states of all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
The enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
The MCLR input provided by the MCLR pin can be dis-
abled with the MCLRE bit in Configuration Register 3H
(CONFIG3H<7>). See Section 23.1 “Configuration
Bits” for more information.
S
R
DS39599C-page 43
Q
Enable OST
Enable PWRT
Chip_Reset
(2)