PIC18F2220 MICROCHIP [Microchip Technology], PIC18F2220 Datasheet - Page 204

• Manufacturer Part Number: PIC18F2220
• Description: 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2220/2320/4220/4320
18.3
In this mode, the USART uses standard Non-Return-
to-Zero (NRZ) format (one Start bit, eight or nine data
bits and one Stop bit). The most common data format
is 8 bits. An on-chip dedicated 8-bit Baud Rate Gener-
ator can be used to derive standard baud rate frequen-
cies from the oscillator. The USART transmits and
receives the LSb first. The USART’s transmitter and
receiver are functionally independent but use the same
data format and baud rate. The Baud Rate Generator
produces a clock, either x16 or x64 of the bit shift rate,
depending on bit BRGH (TXSTA<2>). Parity is not sup-
ported by the hardware but can be implemented in soft-
ware (and stored as the ninth data bit). Asynchronous
mode functions in all power managed modes except
Sleep mode when call clock sources are stopped.
When in PRI_IDLE mode, no changes to the Baud
Rate Generator values are required; however, other
power managed mode clocks may operate at another
frequency than the primary clock. Therefore, the Baud
Rate generator values may need adjusting.
Asynchronous mode is selected by clearing bit, SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 18-1:
DS39599C-page 202
USART Asynchronous Mode
TXIE
Interrupt
TXEN
TXIF
USART TRANSMIT BLOCK DIAGRAM
Baud Rate Generator
SPBRG
Baud Rate CLK
MSb
(8)
TX9D
TSR Register
TX9
TXREG Register
8
Data Bus
18.3.1
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer, TXREG.
The TXREG register is loaded with data in software.
The TSR register is not loaded until the Stop bit has
been transmitted from the previous load. As soon as
the Stop bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one T
flag bit, TXIF (PIR1<4>), is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. Flag bit TXIF is not cleared immediately upon
loading the Transmit Buffer register, TXREG. TXIF
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following
a load of TXREG will return invalid results. While flag bit
TXIF indicated the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. Status bit TRMT is a read-only bit
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit, therefore, the user must poll
this bit in order to determine whether the TSR register
is empty.
Note 1: The TSR register is not mapped in data
LSb
0
2: Flag bit TXIF is set when enable bit TXEN
TRMT
USART ASYNCHRONOUS
TRANSMITTER
memory so it is not available to the user.
is set.
CY
and Control
Pin Buffer
), the TXREG register is empty and
SPEN
 2003 Microchip Technology Inc.
RC6/TX/CK pin