PIC18F2220 MICROCHIP [Microchip Technology], PIC18F2220 Datasheet - Page 165

• Manufacturer Part Number: PIC18F2220
• Description: 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

17.3.8
In Master mode, module clocks may be operating at a
different speed than when in full power mode, or in the
case of the Sleep Power Managed mode, all clocks are
halted.
In most power managed modes, a clock is provided to
the peripherals and is derived from the primary clock
source, the secondary clock (Timer1 oscillator at 32.768
kHz) or the internal oscillator block (one of eight frequen-
cies between 31 kHz and 8 MHz). See Section 2.7
“Clock Sources and Oscillator Switching” for
additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from a power managed mode when the master
completes sending data. If an exit from a power
managed mode is not desired, MSSP interrupts should
be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will pause until
the device wakes from the power managed mode. After
the device returns to full power mode, the module will
resume transmitting and receiving data.
TABLE 17-2:
 2003 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISC
SSPBUF
SSPCON1
TRISA
SSPSTAT
Legend:
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
Name
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
MASTER IN POWER MANAGED
MODES
GIE/GIEH
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
TRISA7
PSPIF
PSPIE
PSPIP
WCOL
Bit 7
SMP
REGISTERS ASSOCIATED WITH SPI OPERATION
(1)
(1)
(1)
(1)
TRISA6
SSPOV
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
CKE
(1)
PORTA Data Direction Register
TMR0IE
SSPEN
RCIF
RCIE
RCIP
Bit 5
D/A
INT0IE
PIC18F2220/2320/4220/4320
Bit 4
TXIF
TXIE
TXIP
CKP
P
SSPM3
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
S
17.3.8.1
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in any power managed mode and
data to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the MSSP
interrupt flag bit will be set and if MSSP interrupts are
enabled, will wake the device from a power managed
mode.
17.3.9
A Reset disables the MSSP module and terminates the
current transfer.
17.3.10
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
There is also an SMP bit which controls when the data
is sampled.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
SSPM2
Standard SPI Mode
Bit 2
R/W
Terminology
0, 0
0, 1
1, 0
1, 1
TMR2IE
TMR2IP
TMR2IF
SSPM1
INT0IF
EFFECTS OF A RESET
BUS MODE COMPATIBILITY
Bit 1
UA
Slave in Power Managed Modes
SPI BUS MODES
TMR1IF
TMR1IE
TMR1IP
SSPM0
RBIF
Bit 0
BF
CKP
Control Bits State
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
--11 1111 --11 1111
0000 0000 0000 0000
POR, BOR
0
0
1
1
Value on
DS39599C-page 163
Value on
all other
CKE
Resets
1
0
1
0