PIC18F2220 MICROCHIP [Microchip Technology], PIC18F2220 Datasheet - Page 239

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PIC18F2220

Manufacturer Part Number
PIC18F2220
Description
28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet

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23.0
PIC18F2X20/4X20 devices include several features
intended to maximize system reliability and minimize
cost through elimination of external components.
These are:
• Oscillator Selection
• Resets:
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers
devices have a Watchdog Timer which is either perma-
nently enabled via the configuration bits or software
controlled (if configured as disabled).
TABLE 23-1:
 2003 Microchip Technology Inc.
300001h
300002h
300003h
300005h
300006h
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note 1:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
File Name
SPECIAL FEATURES OF THE
CPU
provided
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3H MCLRE
CONFIG4L
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
See Register 23-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
CONFIGURATION BITS AND DEVICE IDS
(1)
(1)
for
DEBUG
DEV10
WRTD
DEV2
IESO
Bit 7
CPD
Resets,
EBTRB
WRTB
FSCM
DEV1
DEV9
Bit 6
CPB
PIC18F2X20/4X20
WRTC
DEV0
DEV8
Bit 5
PIC18F2220/2320/4220/4320
WDTPS3 WDTPS2 WDTPS1 WDTPS0
REV4
DEV7
Bit 4
BORV1
EBTR3
F
WRT3
REV3
DEV6
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up while the primary clock source
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate configuration register bits.
23.1
The configuration bits can be programmed (read as ‘0’)
or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh)
which can only be accessed using table reads and
table writes.
Programming the configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
configuration register. In normal operation mode, a
TBLWT instruction with the TBLPTR pointing to the con-
figuration register sets up the address and the data for
the configuration register write. Setting the WR bit
starts a long write to the configuration register. The con-
figuration registers are written a byte at a time. To write
or erase a configuration cell, a TBLWT instruction can
write a ‘1’ or a ‘0’ into the cell. For additional details on
Flash programming, refer to Section 6.5 “Writing to
Flash Program Memory”.
Bit 3
CP3
OSC
3
Configuration Bits
BORV0
EBTR2
F
WRT2
REV2
DEV5
Bit 2
CP2
LVP
OSC
2
EBTR1
F
WRT1
PBAD
REV1
DEV4
Bit 1
BOR
CP1
OSC
1
CCP2MX
EBTR0
PWRT
F
WRT0
STVR
REV0
DEV3
Bit 0
WDT
CP0
OSC
0
DS39599C-page 237
Unprogrammed
11-- 1111
---- 1111
---1 1111
1--- --11
1--- -1-1
---- 1111
11-- ----
---- 1111
111- ----
---- 1111
-1-- ----
xxxx xxxx
0000 0101
Default/
Value
(1)

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