NHPXA270CXXX INTEL [Intel Corporation], NHPXA270CXXX Datasheet - Page 92
NHPXA270CXXX
Manufacturer Part Number
NHPXA270CXXX
Description
Electrical, Mechanical, and Thermal Specification
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.NHPXA270CXXX.pdf
(126 pages)
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Intel® PXA270 Processor
AC Timing Specifications
6-28
Figure 6-17. First-Access Latency Configuration Timing
MD (Code = 2)
MD (Code = 3)
MD (Code = 4)
MD (Code = 5)
MD (Code = 6)
MD (Code = 7)
SDCLK<0>
DQM<3:0>
MA<19:0>
nSDCAS
nCS<0>
Figure 6-17
nSDCAS(ADV), depending on the configuration of the SXCNFG[SXCLx] bit field. The period in
the diagram indicated by different frequency configuration codes (Fcodes or FCCs) is equal to the
number of SDCLK0 cycles between the READ command and the clock edge on which data is
driven onto the bus.
indicates which clock data would be latched following the assertion of
NOTE: CODE = Frequency Configuration Code
Code 2
Code 3
Code 4
Code 5
Valid Address
Electrical, Mechanical, and Thermal Specification
Beat 0
Code 6
0b0000
Code 7
Beat 0
Beat 1
Beat 0
Beat 2
Beat 1
Beat 0
Beat 1 Beat 2
Beat 3 Beat 4
Beat 2 Beat 3
Beat 1
Beat 0
Beat 3
Beat 2
Beat 0
Beat 5
Beat 4
Beat 1
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